公开(公告)号：US20240055300A1

公开(公告)日：2024-02-15

申请号：US17887320

申请日：2022-08-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Ting CHANG ,  Kuo-Ju CHEN ,  Tien-Shun CHANG ,  Su-Hao LIU ,  Huicheng CHANG

IPC分类号： H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L29/66545

摘要： A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

公开(公告)号：US20230387251A1

公开(公告)日：2023-11-30

申请号：US17824690

申请日：2022-05-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tien-Shun CHANG ,  Kuo-Ju CHEN ,  Sih-Jie LIU ,  Wei-Fu WANG ,  Yi-Chao WANG ,  Li-Ting WANG ,  Su-Hao LIU ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/265

摘要： A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.

公开(公告)号：US20230187447A1

公开(公告)日：2023-06-15

申请号：US18106350

申请日：2023-02-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Chang LIN ,  Chun-Feng NIEH ,  Huicheng CHANG ,  Hou-Yu CHEN ,  Yong-Yan LU

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/49

CPC分类号： H01L27/0924 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/6656 ,  H01L21/26593 ,  H01L29/66545 ,  H01L21/823418 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/6681 ,  H01L21/02529 ,  H01L21/823821 ,  H01L21/2658 ,  H01L21/02532 ,  H01L29/7848 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7855 ,  H01L27/1211 ,  H01L21/26513 ,  H01L21/845 ,  H01L21/0262 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/7846 ,  H01L21/823807 ,  H01L21/823412 ,  H01L29/165

摘要： A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20240055480A1

公开(公告)日：2024-02-15

申请号：US17886921

申请日：2022-08-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yun Chen TENG ,  Chen-Fong TSAI ,  Li-Chi YU ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

CPC分类号： H01L29/0673 ,  H01L29/0649 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/7869 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821

摘要： A method includes forming fin structures upwardly extending above a semiconductor substrate; conformally depositing a first dielectric layer over the fin structures; depositing a flowable oxide over the first dielectric layer and between the fin structures; performing, at a temperature lower than about 500° C., a steam annealing process on the flowable oxide to cure the flowable oxide; after performing the steam annealing process, etching the cured flowable oxide until a top surface of the cured flowable oxide is lower than top surfaces of the fin structures; forming a second dielectric layer over the cured flowable oxide; forming a first gate structure extending across a first one of the fin structures and a second gate structure extending across a second one of the fin structures; forming first sources/drain regions on the first one of the fin structures and second sources/drain regions on the second one of the fin structures.

公开(公告)号：US20240006247A1

公开(公告)日：2024-01-04

申请号：US17854997

申请日：2022-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Bau-Ming WANG ,  Liang-Yin CHEN ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823892 ,  H01L21/2652

摘要： A method for manufacturing a semiconductor device includes: forming a first type well in a substrate; and after forming the first type well in the substrate, forming a second type well in the substrate, where the second type well has a conductivity type different from that of the first type well. One of the first and second type wells is formed by sequentially performing multiple ion implantations that use different energies, and one of the ion implantations that uses a lowest energy among the ion implantations is performed first among the ion implantations.

公开(公告)号：US20230260804A1

公开(公告)日：2023-08-17

申请号：US17672144

申请日：2022-02-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jhih-Yong HAN ,  Wen-Yen CHEN ,  Po-Kang HO ,  Tsai-Yu HUANG ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L21/324 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L29/6659

摘要： The method includes performing a well implantation process to dope a dopant into a semiconductor substrate; after performing the well implantation process, performing a flash anneal on the semiconductor substrate, the flash anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200° C. to about 800° C., the first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000° C. to about 1200° C.; after performing the flash anneal, performing a rapid thermal anneal (RTA) on the semiconductor substrate, the RTA including a second preheat step, the first preheat step of the flash anneal being performed for a shorter duration than the second preheat step of the RTA.

公开(公告)号：US20230093608A1

公开(公告)日：2023-03-23

申请号：US17994153

申请日：2022-11-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Po HSIEH ,  Su-Hao LIU ,  Hong-Chih LIU ,  Jing-Huei HUANG ,  Jie-Huang HUANG ,  Lun-Kuang TAN ,  Huicheng CHANG ,  Liang-Yin CHEN ,  Kuo-Ju CHEN

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/532 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417

摘要： A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.

公开(公告)号：US20230395701A1

公开(公告)日：2023-12-07

申请号：US17832306

申请日：2022-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Ming CHEN ,  Szu-Ying CHEN ,  Yen-Chun HUANG ,  Sen-Hong SYUE ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66795 ,  H01L29/7812 ,  H01L29/7869

摘要： A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.

公开(公告)号：US20230299175A1

公开(公告)日：2023-09-21

申请号：US17696257

申请日：2022-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Rui CHEN ,  Yi-Fan CHEN ,  Szu-Ying CHEN ,  Sen-Hong SYUE ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L29/40

CPC分类号： H01L29/66545 ,  H01L21/02211 ,  H01L21/02323 ,  H01L21/02343 ,  H01L29/4983 ,  H01L29/401 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/02337 ,  H01L29/66795

摘要： A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

公开(公告)号：US20240363417A1

公开(公告)日：2024-10-31

申请号：US18768844

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer DHANYAKUMAR ,  Huicheng CHANG ,  Keng-Chu LIN ,  Winnie Victoria Wei-Ning CHEN

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/092

CPC分类号： H01L21/8221 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/092

摘要： A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.