公开(公告)号：US20040038488A1

公开(公告)日：2004-02-26

申请号：US10226283

申请日：2002-08-23

发明人： Chandra Mouli

IPC分类号： H01L021/331 ,  H01L021/00 ,  H01L021/479 ,  H01L021/326 ,  H01L021/84 ,  H01L021/336

CPC分类号： H01L27/10873 ,  H01L21/3003 ,  H01L21/326 ,  H01L21/84 ,  H01L21/86 ,  H01L27/10805 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78612

摘要： The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.

摘要翻译： 本发明提供了一种新的方法，用于在氘退火之前通过在氘退火之前预加压所制造的器件来增加在氘钝化退火期间掺入晶体管器件陷阱位置的氘的量。 本发明的方法同样适用于SOI和CMOS技术。 结果，在工艺流程中在氘退火期间掺入更多的氘可以减少不期望的捕集点的数量。

公开(公告)号：US20010050407A1

公开(公告)日：2001-12-13

申请号：US09873035

申请日：2001-06-02

发明人： Tito Gelsomini ,  Kemal Tamer San

IPC分类号： H01L021/82 ,  H01L021/326 ,  H01L021/479 ,  H01L029/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

摘要翻译： 嵌入在集成电路（IC）中的信息写入寄存器由形成在嵌套在n阱中的隔离p阱中的多个可独立寻址的门控元件构成。 位于p阱上的栅极位于几何形状上的绝缘体上，使得其在施加过应力电压脉冲时局部易于导电，由此二进制信息可以被永久地编码到写寄存器中。 过应力电压脉冲施加在栅极和p阱之间，并且当具有相反极性和较短持续时间的p阱脉冲叠加预定极性和持续时间的写使能脉冲时产生。

公开(公告)号：US20010041460A1

公开(公告)日：2001-11-15

申请号：US09832942

申请日：2001-04-12

发明人： Claire Louise Wiggins

IPC分类号： H01L021/326 ,  H01L021/479 ,  H01L021/31

CPC分类号： H01L21/02266 ,  C23C14/0036 ,  C23C14/083 ,  C23C14/5826 ,  C23C14/5853 ,  H01G4/1254 ,  H01L21/02183 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/31604

摘要： This invention relates to a method of depositing dielectric on a semiconductor substrate to form part of a capacitor. The method includes reactive sputtering a metal oxide layer from a target of metal onto the substrate wherein the support is biased to induce a DC voltage across the depositing dielectric as it forms. The voltage may be in the range of 200-300V.

摘要翻译： 本发明涉及一种在半导体衬底上沉积电介质以形成电容器的一部分的方法。 该方法包括将金属氧化物层从金属靶反应溅射到衬底上，其中支撑体在其形成时被偏置以引导跨越沉积电介质的直流电压。 电压可能在200-300V的范围内。

公开(公告)号：US20040016405A1

公开(公告)日：2004-01-29

申请号：US10205991

申请日：2002-07-26

申请人： Applied Materials, Inc.

发明人： Brad Mays ,  Tetsuya Ishikawa ,  Sergio Fukuda Shoji

IPC分类号： H01L021/66 ,  H01L021/326 ,  H01L021/479 ,  H01L021/306

CPC分类号： H01L21/6833

摘要： A method and apparatus for a mixed-mode operation of an electrostatic chuck in a semiconductor substrate processing system. The chuck is operated in a voltage mode before and after a processing and is operated in a current mode during the processing to suppress arcing during the processing of a substrate.

摘要翻译： 一种用于半导体衬底处理系统中的静电卡盘的混合模式操作的方法和装置。 卡盘在处理之前和之后以电压模式操作，并且在处理期间以电流模式操作以在基板的处理期间抑制电弧。

公开(公告)号：US20030224584A1

公开(公告)日：2003-12-04

申请号：US10413812

申请日：2003-04-15

发明人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schroder ,  Stefan Jakschik ,  Martin Gutsche

IPC分类号： H01L021/326 ,  H01L021/479 ,  H01L021/31 ,  H01L021/469

CPC分类号： H01L21/02238 ,  C25D11/02 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L27/1085

摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

摘要翻译： 用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流 衬底跟随材料在与缺陷相邻的衬底的部分中。 还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。

公开(公告)号：US20020163057A1

公开(公告)日：2002-11-07

申请号：US10139381

申请日：2002-05-07

申请人： Coatue Corporation

发明人： Vladimir Bulovic ,  Aaron Mandell ,  Andrew Perlman

IPC分类号： H01L021/82 ,  H01L021/326 ,  H01L021/479 ,  H01L029/00 ,  H01L021/44

CPC分类号： G11C13/0009 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/13 ,  G11C2213/15 ,  H01L21/76888 ,  H01L23/525 ,  H01L27/105 ,  H01L29/685 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A programmable interconnect structure and method of operating the same provides a programmable interconnection between electrical contacts. The interconnect includes material that has a reversibly programmable resistance. The material includes a molecular matrix with ionic complexes distributed through the molecular matrix. Application of an electrical field or electric current causes the molecular composite material to assume a desired resistivity (or conductivity) state. This state is retained by the molecular composite material to thus form a conductive or a non-conductive path between the electrical contacts.

摘要翻译： 可编程互连结构及其操作方法提供了电触点之间的可编程互连。 互连包括具有可逆可编程电阻的材料。 该材料包括分子矩阵，其中离子配合物分布在分子基质上。 施加电场或电流使得分子复合材料呈现期望的电阻率（或导电性）状态。 该状态由分子复合材料保留，从而在电触点之间形成导电或不导电的路径。

公开(公告)号：US20010049180A1

公开(公告)日：2001-12-06

申请号：US09812702

申请日：2001-03-20

发明人： Gordon C. Taylor ,  Arye Rosen ,  Aly E. Fathy ,  Pradyumna K. Swain ,  Stewart M. Perlow

IPC分类号： H01L021/326 ,  H01L021/479 ,  H01L021/00 ,  H01L021/84

CPC分类号： H01Q1/38 ,  H01L29/868 ,  H01Q9/0407 ,  H01Q21/061 ,  H01Q23/00 ,  H01Q25/00

摘要： A surface PIN (SPIN) device and a method of fabricating such a SPIN device. The SPIN device, when activated, confines carrier injection to a small volume near the surface of the device such that the device is sufficiently conductive to simulate a planar conductor. The SPIN device comprises a Pnull region and an Nnull region formed in an intrinsic (I) layer. The Pnull and Nnull regions are separated by a lateral length of intrinsic material of length L. The length L is approximately the carrier diffusion length. When DC bias is applied across the Nnull and Pnull regions carriers are injected into the intrinsic region at a density exceeding 1018 carriers per cubic cm. The intrinsic region is sufficiently thin to confine the carriers near the surface of the intrinsic region. As such, in the nullonnull state, the SPIN device simulates a conductive material. In the nulloffnull state, the SPIN device is no longer conductive. Consequently, a planar array of SPIN devices can be fabricated and selectively activated to form a dynamic, reconfigurable antenna.

摘要翻译： 表面PIN（SPIN）装置和制造这种SPIN装置的方法。 SPIN装置在被激活时将载流子注入限制在装置表面附近的小体积，使得装置足够导电以模拟平面导体。 SPIN装置包括在本征（I）层中形成的P +区和N +区。 P +和N +区域被长度为L的本征材料的横向长度分开。长度L大约是载流子扩散长度。 当跨越N +和P +区域施加直流偏压时，载流子以超过1018载体/立方厘米的密度注入本征区域。 本征区域足够薄以将载流子限制在本征区域的表面附近。 因此，在“开”状态下，SPIN装置模拟导电材料。 在“关闭”状态下，SPIN设备不再导电。 因此，可以制造并选择性地激活SPIN器件的平面阵列以形成动态的可重新配置的天线。

公开(公告)号：US20040087052A1

公开(公告)日：2004-05-06

申请号：US10345771

申请日：2003-01-16

发明人： Ioannis Katakis ,  Monica Campas Homs

IPC分类号： H01L021/00 ,  H01L021/326 ,  H01L021/479

CPC分类号： G01N33/54393 ,  B01J19/0046 ,  B01J2219/00527 ,  B01J2219/00529 ,  B01J2219/00648 ,  B01J2219/00653 ,  B01J2219/00722 ,  C40B40/06

摘要： A method includes (a) putting a multielectrodic chip lithographed in a wafer that contains between 2 and 2000 individually polarisable electrodes, in contact with a solution or suspension that includes modified colloidal particles with a (bio)chemical recognition element; (b) applying to an electrode of the multielectrodic chip, a potential between null1 and null2V vs. Ag/AgCl saturated, for a period of time between 1 and 300 seconds; (c) washing the chip after this stage (b); and (d) repeat the steps (b) and (c) as many times as needed to deposit a (bio)chemical recognition element, same or different to the one or ones previously deposited, on each one of the electrodes of that chip. The method is applicable for the fabrication of multisensors, particularly in chips and arrays for analytical and diagnostic applications.

摘要翻译： 一种方法包括（a）将包含2至2000个单独可极化电极的晶片中的多电极芯片放置在与包含改性胶体颗粒与（生物）化学识别元件的溶液或悬浮液接触的晶片上; （b）施加到多电极芯片的电极上，在-1和+2V之间的电势与Ag / AgCl饱和的时间在1和300秒之间; （c）在该阶段（b）之后洗涤芯片; 和（d）根据需要重复步骤（b）和（c），以沉积与该芯片的每个电极相同或不同于之前沉积的一个或多个的（生物）化学识别元件。 该方法适用于制造多传感器，特别是用于分析和诊断应用的芯片和阵列。

公开(公告)号：US20030036250A1

公开(公告)日：2003-02-20

申请号：US10005270

申请日：2001-12-04

发明人： Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： H01L021/326 ,  H01L021/479 ,  H01L021/31

CPC分类号： G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

摘要翻译： 一种用于操作具有位于衬底上的电荷俘获层的P沟道SONOS存储器件的方法，位于俘获层上的栅电极，位于电荷俘获层每侧的衬底中的两个掺杂区。 两个掺杂区域被设置为漏极区域和源极区域。 当需要编程动作时，栅极电极和漏极区域被施加第一负的高电平偏置，并且源区域和衬底被施加接地电压。 当需要擦除动作时，栅电极是比绝对值中的第一负电压小的第二负偏压。 同时，漏极区域被施加第三负偏压，并且衬底被施加接地电压。 第三负电压大于绝对值中的第二负偏压。

公开(公告)号：US20020166570A1

公开(公告)日：2002-11-14

申请号：US09871534

申请日：2001-05-31

发明人： Chung-Tai Chen

IPC分类号： B08B003/08 ,  H01L021/302 ,  H01L021/461 ,  H01L021/311 ,  H01L021/326 ,  H01L021/479

CPC分类号： H01L21/02071 ,  B08B3/10

摘要： A cleaning method for semiconductor manufacturing process. A to-be-cleaned wafer having a metal layer thereon is provided. The wafer is placed into a chemical cleaning equipment unit to clean the wafer surface with a chemical cleaning solution while protecting the metal layer by a cathodic protection method. Next, the chemical cleaning solution on the wafer surface is rinsed away and the wafer is then dried to complete the cleaning method.

摘要翻译： 一种半导体制造工艺的清洗方法。 提供其上具有金属层的待清洁晶片。 将晶片放置在化学清洁设备单元中以用化学清洁溶液清洁晶片表面，同时通过阴极保护方法保护金属层。 接下来，将晶片表面上的化学清洁溶液冲洗掉，然后干燥晶片以完成清洁方法。