公开(公告)号：US20040129994A1

公开(公告)日：2004-07-08

申请号：US10697129

申请日：2003-10-29

申请人： Acrorad Co., Ltd.

发明人： Miki Moriyama ,  Masaki Murakami ,  Atsushi Kyan ,  Ryoichi Ohno

IPC分类号： H01L027/095

CPC分类号： H01L31/022408 ,  H01L31/0296 ,  H01L31/032 ,  H01L31/118

摘要： Disclosed is a semiconductor radiation detector element of Schottky barrier type, comprising: a compound semiconductor crystal including cadmium and tellurium as main components; and voltage application means for applying voltage to the compound semiconductor crystal. According to the present invention, said voltage application means includes a compound of indium, cadmium and tellurium: InxCdyTez formed on one surface of the compound semiconductor crystal. Preferably, the rate nullznull of occupation of tellurium in the compound InxCdyTez is in the range of not less than 42.9%, but not greater than 50% by ratio of number of atoms. Furthermore, preferably, the rate nullynull of occupation of cadmium in the compound InxCdyTez is in the range of not less than 0%, but not greater than 10% by ratio of number of atoms.

摘要翻译： 公开了一种肖特基势垒型半导体辐射检测元件，其特征在于，包括：以镉和碲为主要成分的化合物半导体晶体; 以及用于向化合物半导体晶体施加电压的电压施加装置。 根据本发明，所述电压施加装置包括在化合物半导体晶体的一个表面上形成的铟，镉和碲化合物：In x C y Te Tez。 优选地，化合物InxCdyTez中碲的占据率“z”在原子数之比不小于42.9％但不大于50％的范围内。 此外，化合物InxCdyTez中的镉的占有率优选为y以上，以原子数比计为0％以上10％以下的范围。

公开(公告)号：US20040089908A1

公开(公告)日：2004-05-13

申请号：US10696136

申请日：2003-10-29

发明人： John Charles Desko ,  Michael J. Evans ,  Chung-Ming Hsieh ,  Tzu-Yen Hsieh ,  Bailey R. Jones ,  Thomas J. Krutsick ,  John Michael Siket JR. ,  Brian Eric Thompson ,  Steven W. Wallace

IPC分类号： H01L027/095 ,  H01L029/47 ,  H01L031/07 ,  H01L021/44

CPC分类号： H01L29/402 ,  H01L29/872

摘要： A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.

摘要翻译： 通过一系列制造步骤制造肖特基二极管。 定义半导体衬底的有源区，其中制造肖特基二极管。 至少第一和第二层绝缘材料施加在有效区域上。 在有源区域上施加具有第一蚀刻速率的第一绝缘材料层。 具有第二，更大蚀刻速率的第二层绝缘材料施加在绝缘材料的第一层上，其厚度约为第一绝缘材料层厚度的两倍。 对绝缘材料进行图案化，并且通过绝缘材料层蚀刻窗口到半导体衬底。 金属被施加并且不需要的金属被蚀刻掉，留下窗口中的金属在其中形成肖特基接触。 可以采用一个或多个阻挡层。

公开(公告)号：US20040061194A1

公开(公告)日：2004-04-01

申请号：US10453045

申请日：2003-06-03

发明人： Yoshito Ikeda ,  Kaoru Inoue ,  Yutaka Hirose ,  Katsunori Nishii

IPC分类号： H01L027/095

CPC分类号： H01L29/66871 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/812

摘要： A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.

摘要翻译： 在蓝宝石衬底上形成缓冲层，未掺杂的氮化镓层和n型氮化镓活性层。 然后分别在作为源极接触，漏极接触和栅极接触的n型氮化镓有源层上形成欧姆接触和肖特基接触。 肖特基接触是铜合金，例如钯铜，其中铜的重量含量为5％。

公开(公告)号：US20040016984A1

公开(公告)日：2004-01-29

申请号：US10200118

申请日：2002-07-23

申请人： National Chiao Tung University

发明人： Cheng-Shih Lee ,  Yi Chang

IPC分类号： H01L027/095

CPC分类号： H01L29/66863 ,  H01L23/4821 ,  H01L27/0605 ,  H01L29/475 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a Schottky Structure in gallium arsenide (GaAs) semiconductor device, which comprises a gallium arsenide (GaAs) semiconductor substrate, a titanium (Ti) layer on a surface of said gallium arsenide (GaAs) semiconductor substrate to form Schottky contact, a diffusion barrier layer on a surface of said titanium (Ti) layer to block metal diffusion, and a first copper layer on a surface of said diffusion barrier layer.

公开(公告)号：US20030116847A1

公开(公告)日：2003-06-26

申请号：US10320048

申请日：2002-12-16

发明人： Chang Shuk Kim

IPC分类号： H01L027/095

CPC分类号： H01L27/224

摘要： A magnetic random access memory (MRAM) using a schottky diode is disclosed. In order to achieve high integration of the memory device, a word line is formed on a semiconductor substrate without using a connection layer and a stacked structure including an MTJ cell, a semiconductor layer and a bit line is formed on the word line, thereby forming the schottky diode between the MTJ cell and the bit line. As a result, a structure of the device is simplified, and the device may be highly integrated due to repeated stacking.

摘要翻译： 公开了一种使用肖特基二极管的磁性随机存取存储器（MRAM）。 为了实现存储器件的高度集成，在半导体衬底上形成字线而不使用连接层，并且在字线上形成包括MTJ单元，半导体层和位线的堆叠结构，从而形成 在MTJ单元和位线之间的肖特基二极管。 结果，简化了装置的结构，并且由于重复堆叠，装置可以高度集成。

公开(公告)号：US20030020135A1

公开(公告)日：2003-01-30

申请号：US10237106

申请日：2002-09-09

申请人： DaimlerChrysler AG

发明人： Nando Kaminski ,  Raban Held

IPC分类号： H01L027/095

CPC分类号： H01L29/6606 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/475 ,  H01L29/861 ,  H01L29/872

摘要： A method for producing a semiconductor component with adjacent Schottky (5) and pn (9) junctions positions in a drift area (2, 10) of a semiconductor material. According to the method, a silicon carbide substrate doped with a first doping material of at least 1018 cmnull3 is provided, and a silicon carbide layer with a second doping material of the same charge carrier type in the range of 1014 and 1017 cmnull3 is homo-epitaxially deposited on the substrate. A third doping material with a complimentary charge carrier is inserted, and structured with the aid of a diffusion and/or ion implantation, on the silicon carbide layer surface that is arranged far from the substrate to form pn junctions. Subsequently the component is subjected to a first temperature treatment between 1400null C. and 1700null C. Following this temperature treatment, a first metal coating is deposited on the implanted surface in order to form a Schottky contact and then a second metal coating is deposited in order to form an ohmic contact. Subsequently the first and second metal coatings are structured as designed.

摘要翻译： 一种在半导体材料的漂移区域（2,10）中制造具有相邻肖特基（5）和pn（9）结的半导体部件的方法。 根据该方法，提供掺杂有至少1018cm-3的第一掺杂材料的碳化硅衬底，并且具有相同电荷载流子型的第二掺杂材料的碳化硅层在1014和1017cm- 3同基因外延沉积在基底上。 插入具有互补电荷载体的第三掺杂材料，并且借助于扩散和/或离子注入而构造在碳化硅层表面上，其布置成远离衬底以形成pn结。 随后，将组分在1400℃和1700℃之间进行第一温度处理。在该温度处理之后，在注入的表面上沉积第一金属涂层以形成肖特基接触，然后沉积第二金属涂层 以形成欧姆接触。 随后，第一和第二金属涂层按照设计构造。

公开(公告)号：US20020179993A1

公开(公告)日：2002-12-05

申请号：US09872926

申请日：2001-06-01

发明人： Fwu-Iuan Hshieh ,  Koon Chong So

IPC分类号： H01L027/095 ,  H01L029/47 ,  H01L029/812 ,  H01L031/07 ,  H01L031/108

CPC分类号： H01L29/417 ,  H01L27/0817 ,  H01L27/095 ,  H01L29/42364 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/8725

摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

公开(公告)号：US20020163012A1

公开(公告)日：2002-11-07

申请号：US09746064

申请日：2000-12-26

申请人： FUJITSU LIMITED

发明人： Mizuhisa Nihei ,  Yuu Watanabe

IPC分类号： H01L031/072 ,  H01L027/095 ,  H01L023/48

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/812

摘要： A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

摘要翻译： 半导体三极管包括设置在沟道层上的栅电极，其中在沟道层的顶表面和栅电极之间插入绝缘金属氧化物层。

公开(公告)号：US20020074613A1

公开(公告)日：2002-06-20

申请号：US09737357

申请日：2000-12-15

发明人： Fwu-Iuan Hshieh ,  Koon Chong So ,  John E. Amato

IPC分类号： H01L027/095

CPC分类号： H01L29/66143 ,  H01L29/417 ,  H01L29/872

摘要： A trench Schottky barrier rectifier and a method of making the same are disclosed. The rectifier comprises: (a) A semiconductor region having first and second opposing faces. The semiconductor region comprises a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face. The drift region has a lower net doping concentration than that of the cathode region. (b) A plurality of trenches extending into the semiconductor region from the first face. The trenches define a plurality of mesas within the semiconductor region, and the trenches form a plurality of trench intersections. (c) An oxide layer covering the semiconductor region on bottoms of the trenches and on lower portions of sidewalls of the trenches. (d) A polysilicon region disposed over the oxide layer within the trenches. (e) Insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.

摘要翻译： 公开了一种沟槽肖特基势垒整流器及其制造方法。 整流器包括：（a）具有第一和第二相对面的半导体区域。 半导体区域包括与第一面相邻的第一导电类型的漂移区域和与第二面相邻的第一导电类型的阴极区域。 漂移区具有比阴极区更低的净掺杂浓度。 （b）从第一面延伸到半导体区域的多个沟槽。 沟槽在半导体区域内限定多个台面，并且沟槽形成多个沟槽交叉点。 （c）覆盖沟槽底部和沟槽侧壁下部的半导体区域的氧化物层。 （d）设置在沟槽内的氧化物层上的多晶硅区域。 （e）覆盖多晶硅区域的一部分和氧化物层的一部分的沟槽交点处的绝缘区域。

公开(公告)号：US20040232509A1

公开(公告)日：2004-11-25

申请号：US10440882

申请日：2003-05-19

申请人： MATRIX SEMICONDUCTOR, Inc.

发明人： Michael A. Vyvoda

IPC分类号： H01L027/095

CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  Y10S257/91 ,  H01L2924/00

摘要： A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are nullrightside-upnull with antifuse over the metal, and those on even levels are nullupside downnull with metal over the antifuse. Both antifuses are preferably grown oxides.

摘要翻译： 公开了包括由反熔丝分离的肖特基二极管部件的单片三维存储器阵列。 肖特基二极管是垂直取向的并且设置在交替的电平上。 那些在奇怪的层面上是金属上的反熔丝是“右起”的，而平均层次上的那些是反金属的“颠倒”的。 两种反熔点优选是生长的氧化物。