公开(公告)号：US20040262702A1

公开(公告)日：2004-12-30

申请号：US10611245

申请日：2003-06-30

申请人： MATRIX SEMICONDUCTOR, INC.

发明人： S. Brad Herner

IPC分类号： H01L029/76

CPC分类号： H01L23/5252 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/3205 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.

摘要翻译： 当与电介质耦合时，PVD溅射沉积材料（优选氮化钛）的低密度，高电阻率层产生用于半导体器件的优异的低漏电绝缘屏障。 该材料是通过溅射方法产生的，这些方法使离子以较低的能量冲击沉积表面，例如在离子金属等离子体室中，没有自偏压加速垂直于沉积表面的离子，或者在具有压力增加的标准PVD室中 。

公开(公告)号：US20040232509A1

公开(公告)日：2004-11-25

申请号：US10440882

申请日：2003-05-19

申请人： MATRIX SEMICONDUCTOR, Inc.

发明人： Michael A. Vyvoda

IPC分类号： H01L027/095

CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  Y10S257/91 ,  H01L2924/00

摘要： A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are nullrightside-upnull with antifuse over the metal, and those on even levels are nullupside downnull with metal over the antifuse. Both antifuses are preferably grown oxides.

摘要翻译： 公开了包括由反熔丝分离的肖特基二极管部件的单片三维存储器阵列。 肖特基二极管是垂直取向的并且设置在交替的电平上。 那些在奇怪的层面上是金属上的反熔丝是“右起”的，而平均层次上的那些是反金属的“颠倒”的。 两种反熔点优选是生长的氧化物。

公开(公告)号：US20040206996A1

公开(公告)日：2004-10-21

申请号：US10842008

申请日：2004-05-10

申请人： Matrix Semiconductor, Inc.

发明人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

IPC分类号： H01L021/8242

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US20030206429A2

公开(公告)日：2003-11-06

申请号：US09939498

申请日：2001-08-24

申请人： Matrix Semiconductor, Inc.

发明人： Vivek Subramanian ,  James M. Cleeves

IPC分类号： G11C017/00

CPC分类号： G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

摘要： Abstract of DisclosureA very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with Nnull1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

摘要翻译： 公开摘要公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：US20030202404A1

公开(公告)日：2003-10-30

申请号：US10440377

申请日：2003-05-16

申请人： Matrix Semiconductor, Inc.

发明人： Roy E. Scheuerlein

IPC分类号： G11C005/02

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C8/08 ,  G11C17/18 ,  G11C2207/063

摘要： The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

摘要翻译： 本文描述的优选实施例提供了一种存储器件，其具有在多个存储器阵列下以棋盘图案布置的行和列解码器电路。 在一个优选实施例中，存储器件具有其排列在多个存储器阵列下的棋盘图案中的行解码器电路和列解码器电路。 因为行解码器和列解码器电路中的每一个都与其位置上方的存储器阵列和相邻阵列相关联，所以与现有方法相比，提供了更密集的支持电路装置。 提供了其它优选实施方案，并且本文所述的各优选实施方案可以单独使用或彼此组合使用。

公开(公告)号：US20030057435A1

公开(公告)日：2003-03-27

申请号：US09961278

申请日：2001-09-25

申请人： Matrix Semiconductor, Inc.

发明人： Andrew J. Walker

IPC分类号： H01L029/74

CPC分类号： H01L27/112 ,  H01L27/0688 ,  H01L27/12

摘要： There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode and a gate insulating layer between the gate electrode and the channel region. The device also contains a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type. An intrinsic or lightly doped semiconductor drain offset region is located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.

摘要翻译： 提供了具有垂直漏极偏移区域的诸如TFT的半导体器件。 该器件包含具有上部第一表面，第一表面上的第一导电类型的半导体沟道区，栅电极和栅极电极与沟道区之间的栅极绝缘层的衬底。 该器件还包含第二导电类型的重掺杂半导体源极区域，第二导电类型的重掺杂半导体漏极区域。 本征或轻掺杂的半导体漏极偏移区域位于漏极区域和沟道区域之间，使得漏极区域至少部分地在垂直于第一表面的方向上偏离沟道区域。

公开(公告)号：US20030026158A1

公开(公告)日：2003-02-06

申请号：US10027466

申请日：2001-12-20

申请人： Matrix Semiconductor, Inc.

发明人： N. Johan Knall ,  James M. Cleeves ,  Igor G. Kouznetsov ,  Michael A. Vyvoda

IPC分类号： G11C011/36 ,  G11C005/00

CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 null and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.

摘要翻译： 用于二维或三维存储器阵列的存储单元包括位于导体之间的第一和第二导体和一组层。 这组层包括厚度小于35的介质断裂抗熔融层和在2V时大于1mA / cm 2的漏电流密度（在未破裂状态下）。这种低厚度和高电流泄漏密度提供了一种 具有不对称介质层的存储单元击穿电压特性。 反熔丝层由反熔丝材料形成，其特征在于厚度Tminmin，其中反熔丝材料被最小数量的具有反向偏置存储单元中包含的二极管组件的极性的写入脉冲破裂。 反熔丝层的平均厚度T小于厚度Tminlife。

公开(公告)号：US20040266206A1

公开(公告)日：2004-12-30

申请号：US10611246

申请日：2003-06-30

申请人： MATRIX SEMICONDUCTOR, INC.

发明人： James M. Cleeves

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11578

摘要： A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present invention can be substantially the same as the minimum feature size, even at very small minimum feature size.

摘要翻译： 一种形成有利于高密度半导体器件的垂直互连的方法。 形成优选硅化钴的导电蚀刻停止层。 蚀刻停止层可以是图案化线或线的形式。 接触材料层形成在蚀刻停止层上并与蚀刻停止层接触。 图案化接触材料层以形成柱。 电介质沉积在柱之间和之间，然后将电介质平坦化以暴露柱的顶部。 柱可以用作垂直互连，其将形成在垂直互连上的下一个导电层与下面的蚀刻停止层电连接。 根据本发明形成的垂直互连的图案尺寸可以与最小特征尺寸基本相同，即使在非常小的最小特征尺寸。

公开(公告)号：US20040177229A1

公开(公告)日：2004-09-09

申请号：US10806826

申请日：2004-03-22

申请人： Matrix Semiconductor, Inc.

发明人： Roger W. March ,  Christopher S. Moore ,  Daniel T. Brown

IPC分类号： G06F012/00

CPC分类号： G06F11/1008 ,  G06F3/0601 ,  G06F3/08 ,  G06F2003/0697 ,  G11C17/00 ,  Y10S707/99934 ,  Y10S707/99943 ,  Y10S707/99953 ,  Y10S707/99956

摘要： The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition. Additionally, methods for permanently preventing modification of data stored in a memory device and for identifying memory cells storing data are disclosed.

公开(公告)号：US20040145005A1

公开(公告)日：2004-07-29

申请号：US10756356

申请日：2004-01-14

申请人： MATRIX SEMICONDUCTOR, INC.

发明人： Michael A. Vyvoda

IPC分类号： H01L027/108

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/12 ,  H01L27/1214 ,  H01L29/7881

摘要： A semiconductor device contains a word line, a charge storage region located above the word line, an active layer located above the charge storage region, a patterned etch stop layer located above a first portion of the active layer, and bit lines located over a portion of the etch stop layer and over second portions of the active layer.