公开(公告)号：US06781239B1

公开(公告)日：2004-08-24

申请号：US10010343

申请日：2001-12-05

申请人： Visvamohan Yegnashankaran ,  Gobi R. Padmanabhan

发明人： Visvamohan Yegnashankaran ,  Gobi R. Padmanabhan

IPC分类号： H01L2316

CPC分类号： H01L23/66 ,  H01F17/0006 ,  H01F27/292 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electrically connected to the first die as a flip chip.

摘要翻译： 公开了一种具有高Q电感和电容器的半导体集成电路。 半导体电路形成在第一管芯上，而具有电感和电容的微机电结构形成在第二管芯上。 第二管芯作为倒装芯片被附接并电连接到第一管芯。

公开(公告)号：US06225687B1

公开(公告)日：2001-05-01

申请号：US09388768

申请日：1999-09-02

申请人： Dustin P. Wood

发明人： Dustin P. Wood

IPC分类号： H01L2316

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

摘要： A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

摘要翻译： 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。