公开(公告)号：US10242942B2

公开(公告)日：2019-03-26

申请号：US15127708

申请日：2014-04-25

申请人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

发明人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US06831233B2

公开(公告)日：2004-12-14

申请号：US09800703

申请日：2001-03-07

申请人： Dustin P. Wood

发明人： Dustin P. Wood

IPC分类号： H05K100

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

摘要： A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

摘要翻译： 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。

公开(公告)号：US07667320B2

公开(公告)日：2010-02-23

申请号：US12022254

申请日：2008-01-30

申请人： Dustin P. Wood ,  Kaladhar Radhakrishnan

发明人： Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC分类号： H01L23/34

CPC分类号： H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0262 ,  H05K2201/10325 ,  H05K2201/10719

摘要： An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

摘要翻译： 集成电路（IC）封装包括安装在基板的第一侧上的基板和IC芯片。 IC封装还包括安装在基板的第二侧上的多个电容器。 第二面与第一面相反。 该IC封装还包括多个导电接触焊盘，其形成在该衬底的第二侧上并散布在该电容器之间。 描述和要求保护其他实施例。

公开(公告)号：US07463492B2

公开(公告)日：2008-12-09

申请号：US11823522

申请日：2007-06-26

申请人： Kaladhar Radhakrishnan ,  Dustin P. Wood ,  Nicholas L. Holmberg

发明人： Kaladhar Radhakrishnan ,  Dustin P. Wood ,  Nicholas L. Holmberg

IPC分类号： H05K7/00

CPC分类号： H01G4/242 ,  H01G2/06 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L2224/16225 ,  H01L2924/14

摘要： An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

摘要翻译： 描述了与安装在IC封装上的集成电路（IC）一起使用的阵列电容器。 阵列电容器包括与多个第二导电层交错的多个第一导电层和分隔相邻导电层的多个电介质层。 阵列电容器还包括多个用于电连接第一导电层的第一导电通孔和多个第二导电通孔，以电连接第二导电层。 阵列电容器设置有开口，其被配置为使得IC封装的引脚能够通过。

公开(公告)号：US07339263B2

公开(公告)日：2008-03-04

申请号：US10880150

申请日：2004-06-28

申请人： Brent S. Stone ,  Dustin P. Wood ,  Kaladhar Radhakrishnan

发明人： Brent S. Stone ,  Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC分类号： H01L23/02

CPC分类号： H01L23/50 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

摘要翻译： 集成电路封装包括由衬底的表面支撑的第一电容器和由衬底的表面支撑的第二电容器。 第一电容器在阴影区域内，第二电容器位于阴影阴影区域的外部。

公开(公告)号：US07755165B2

公开(公告)日：2010-07-13

申请号：US11972583

申请日：2008-01-10

申请人： Cengiz A. Palanduz ,  Dustin P. Wood

发明人： Cengiz A. Palanduz ,  Dustin P. Wood

IPC分类号： H01L29/00

CPC分类号： H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

摘要： A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

摘要翻译： 一种方法，包括将包含一定量的陶瓷材料的纳米颗粒的胶体悬浮液沉积在基底上; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括计算设备的系统，包括微处理器，所述微处理器通过衬底耦合到印刷电路板，所述衬底包括形成在表面上的至少一个电容器结构，所述电容器结构包括第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料包括柱状晶粒。

公开(公告)号：US07495336B2

公开(公告)日：2009-02-24

申请号：US11322384

申请日：2005-12-30

申请人： Joel A. Auernheimer ,  Nicholas Holmberg ,  Kaladhar Radhakrishnan ,  Dustin P. Wood

发明人： Joel A. Auernheimer ,  Nicholas Holmberg ,  Kaladhar Radhakrishnan ,  Dustin P. Wood

IPC分类号： H01L29/00

CPC分类号： H01L23/49822 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15312 ,  Y10S257/924 ,  H01L2224/05599

摘要： An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.

摘要翻译： 集成宽带阵列电容器包括具有变化的电容和响应时间的至少两个区域。 宽带阵列电容器在一个插座上是一次性的，或者与插座成一体。 操作宽带阵列电容器的方法包括响应于至少两个区域中的每一个的负载瞬变。 还公开了包括宽带阵列电容器的计算系统。

公开(公告)号：US07375412B1

公开(公告)日：2008-05-20

申请号：US11096313

申请日：2005-03-31

申请人： Cengiz A. Palanduz ,  Dustin P. Wood

发明人： Cengiz A. Palanduz ,  Dustin P. Wood

IPC分类号： H01L29/00

CPC分类号： H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

摘要： A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

摘要翻译： 一种方法，包括将包含一定量的陶瓷材料的纳米颗粒的胶体悬浮液沉积在基底上; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括计算设备的系统，包括微处理器，所述微处理器通过衬底耦合到印刷电路板，所述衬底包括形成在表面上的至少一个电容器结构，所述电容器结构包括第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料包括柱状晶粒。

公开(公告)号：US07365428B2

公开(公告)日：2008-04-29

申请号：US10971379

申请日：2004-10-22

申请人： Joel A. Auernheimer ,  Nicholas L. Holmberg ,  Kaladhar Radhakrishnan ,  Dustin P. Wood

发明人： Joel A. Auernheimer ,  Nicholas L. Holmberg ,  Kaladhar Radhakrishnan ,  Dustin P. Wood

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L27/06 ,  H01L27/07 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L23/50 ,  H01G4/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/023 ,  H01L2224/0401

摘要： An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.

摘要翻译： 一种装置包括设置在装置的第一侧上的第一多个触点，适于与外部集成电路封装上的第一对应的多个触点接合。 该装置还包括选择性地耦合到第一多个触点，一个或多个迹线和布置在第一侧上的第二多个触点的多个电容存储结构。 第二多个触点适于与外部集成电路封装上的第二对应的多个触点接合，其中第二多个触点中的至少两个触头适于耦合到至少一个或多个迹线的第一迹线 以形成第一电阻结构。

公开(公告)号：US07208830B2

公开(公告)日：2007-04-24

申请号：US10883419

申请日：2004-06-30

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

IPC分类号： H01L23/48

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

摘要翻译： 在本发明的一个实施例中，集成电路封装包括集成电路，封装基板，第一凸块，第二凸块和分流器，以提供电流分配和可靠性冗余。 第一和第二凸起在集成电路和封装衬底之间提供第一和第二电流通路。 分流器在第一凸块和第二凸块之间提供第三电流通路。