公开(公告)号：US12073902B2

公开(公告)日：2024-08-27

申请号：US18077795

申请日：2022-12-08

申请人： SK hynix Inc.

发明人： Kyung Whan Kim ,  Sun Hwa Park ,  Kee Yun Kim ,  Sung Joo Ha ,  Ah Reum Han

IPC分类号： G11C29/42 ,  G06F11/14 ,  G11C29/00 ,  G11C29/18 ,  G11C29/30 ,  G11C29/44

CPC分类号： G11C29/42 ,  G06F11/1451 ,  G06F11/1469 ,  G11C29/30 ,  G11C29/44 ,  G11C29/702 ,  G11C29/785 ,  G11C2029/1802

摘要： A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

公开(公告)号：US10896738B1

公开(公告)日：2021-01-19

申请号：US16590694

申请日：2019-10-02

申请人： MICRON TECHNOLOGY, INC.

发明人： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

IPC分类号： G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/30 ,  G11C29/36 ,  G11C29/12

摘要： Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

公开(公告)号：US10453547B2

公开(公告)日：2019-10-22

申请号：US15625313

申请日：2017-06-16

申请人： Seagate Technology LLC

发明人： Darshana H. Mehta ,  Antoine Khoueir ,  Ara Patapoutian

IPC分类号： G11C29/00 ,  G11C29/10 ,  G11C29/30 ,  G11C29/42 ,  G06F12/02 ,  G06F3/06 ,  G11C29/44 ,  G11C29/52 ,  G11C29/32

摘要： Systems and methods presented herein provide for monitoring block, page, and/or stripe degradation. In one embodiment, a controller is operable to scan a first block of memory to identify a failure in a portion of the first block. The controller suspends input/output (I/O) operations to the failed portion of the first block, and tests the failed portion of the first block to determine if the failure is a transient failure. Testing includes loading the portion of the first block with data, and reading the data from the loaded portion of the first block. If the failure subsides after testing, the controller is further operable to determine that the failure is a transient failure, and to resume I/O operations to the portion of the first block.

公开(公告)号：US10365328B2

公开(公告)日：2019-07-30

申请号：US15636793

申请日：2017-06-29

申请人： GLOBALFOUNDRIES INC.

发明人： Jian Sun ,  Chao Meng ,  Xiaoxiao Li ,  Yinpeng Lu

IPC分类号： G01R31/00 ,  G01R31/3185 ,  G11C29/30 ,  G06F11/22 ,  H03K19/177 ,  H03K19/173 ,  G11C29/12 ,  G11C29/32

摘要： A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

公开(公告)号：US20190004114A1

公开(公告)日：2019-01-03

申请号：US15636793

申请日：2017-06-29

申请人： GLOBALFOUNDRIES INC.

发明人： JIAN SUN ,  CHAO MENG ,  XIAOXIAO LI ,  YINPENG LU

IPC分类号： G01R31/3185 ,  G11C29/30 ,  G06F11/22 ,  H03K19/177 ,  H03K19/173

CPC分类号： G01R31/318536 ,  G01R31/318505 ,  G06F11/2205 ,  G11C29/12015 ,  G11C29/30 ,  G11C29/32 ,  G11C2029/3202 ,  H03K19/1735 ,  H03K19/1776

摘要： A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

公开(公告)号：US10094869B2

公开(公告)日：2018-10-09

申请号：US15650451

申请日：2017-07-14

申请人： SK hynix Inc.

发明人： Sang Hee Kim

IPC分类号： G01R31/28 ,  G11C29/44 ,  G11C29/20 ,  G11C29/00 ,  G11C29/24 ,  G11C29/30 ,  G11C17/16

摘要： A repair device and a semiconductor device including the same are disclosed, which relate to a technology for storing failure information in a fuse circuit during a test operation. The repair device includes a test circuit configured to test data received from a cell array in response to a test signal, and output a failure signal when a failure occurs. The repair device also includes a count circuit configured to output a counting signal by counting the failure signal, a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal. Further, the repair device includes a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated, and a column fuse circuit configured to sequentially store the column address.

公开(公告)号：US07821226B2

公开(公告)日：2010-10-26

申请号：US12371318

申请日：2009-02-13

申请人： Joachim Froeschl

发明人： Joachim Froeschl

IPC分类号： H02J7/14 ,  G11C29/30 ,  G11C15/04 ,  G01R31/28

CPC分类号： G01R31/3658 ,  G11C2029/0409 ,  H01M10/482

摘要： A method for placing addresses in the memory cells of a rechargeable energy storage device for use in a motor vehicle, each of which memory cells includes at least one sensor device and an individualizing device for storing an address. In order to optimize the placing of addresses in the memory cells of a rechargeable storage device, the functionality of the memory cells is checked using the sensor device in the vehicle, an individual address is assigned to each operable memory cell, and the individual address is used to individualize the sensor values made available from the sensor device.

摘要翻译： 一种将地址放置在用于机动车辆的可再充电能量存储装置的存储单元中的方法，每个存储单元包括至少一个传感器装置和用于存储地址的个性化装置。 为了优化地址在可再充电存储设备的存储单元中的放置，使用车辆中的传感器设备检查存储器单元的功能，将单独的地址分配给每个可操作的存储器单元，并且单个地址是 用于个别化从传感器设备获得的传感器值。

公开(公告)号：US07106641B2

公开(公告)日：2006-09-12

申请号：US11064837

申请日：2005-02-25

申请人： Shuichi Tsukada

发明人： Shuichi Tsukada

IPC分类号： G11C29/30

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C11/4094 ,  G11C29/83 ,  G11C2207/2227

摘要： To provide a dynamic semiconductor memory device wherein it is possible to perform a reliable redundancy relief with a small layout area and high redundancy relieving rate while properly dealing with the standby current fault caused by a short-circuit defect between a bit line and word line. A common current-limiting element is provided for an equalizer circuit for a bit line pair on one side and another equalizer circuit for another bit line pair on the other side in a shared sense amplifier, and a bit line precharge potential is supplied to the equalizer circuits on the both sides through the current-limiting element.

摘要翻译： 提供一种动态半导体存储器件，其中可以在正确处理由位线和字线之间的短路缺陷引起的待机电流故障的同时，以小的布局面积和高的冗余缓解率执行可靠的冗余度。 一个公共限流元件用于位于一侧的位线对的均衡器电路和用于共享读出放大器另一侧的另一个位线对的另一个均衡器电路，位线预充电电位被提供给均衡器 两侧的电路通过限流元件。

公开(公告)号：US6119257A

公开(公告)日：2000-09-12

申请号：US27473

申请日：1998-02-20

申请人： Toshiyuki Negishi

发明人： Toshiyuki Negishi

IPC分类号： G01R31/3183 ,  G01R31/319 ,  G01R31/3193 ,  G11C29/30 ,  G11C29/56 ,  G01R31/28

CPC分类号： G11C29/56004 ,  G01R31/31919 ,  G01R31/31935 ,  G11C29/30 ,  G11C29/56 ,  G11C29/56012 ,  G11C2029/5602

摘要： An IC tester is provided which is capable of performing a high speed test of an IC under test without using a plurality of pin units for one pin of the IC under test. For each of pins of an IC under test are provided first and second two pattern generators first and second waveform shaping devices having waveform memories and respectively, first and second logical comparators and first and second failure analysis memories. Odd addresses of the first waveform memory are accessed by the first pattern generator, even addresses of the second waveform memory are accessed by the second pattern generator, and waveform data from these two waveform shaping devices are multiplexed for half of the period of a test pattern signal of the normal speed to set and reset first and scond set/reset flip-flops SRFF1 and SRFF2. As a result, a test pattern signal of high speed of twice the normal speed is produced and a test of an IC under test is implemented at high speed of twice the normal speed.

摘要翻译： 提供一种IC测试器，其能够对被测试IC的一个引脚不使用多个引脚单元进行测试的IC的高速测试。 第一和第二两个图案生成器的第一和第二波形整形装置分别具有波形存储器，第一和第二逻辑比较器以及第一和第二故障分析存储器。 第一波形存储器的奇地址由第一模式发生器访问，第二波形存储器的偶数地址由第二模式发生器访问，并且来自这两个波形整形装置的波形数据被复用为测试模式的一半周期 首先设置和复位正常速度的信号，并且设置/复位触发器SRFF1和SRFF2。 结果，产生了正常速度的两倍的高速度的测试图形信号，并且以正常速度的两倍的高速度实施被测试的IC的测试。

公开(公告)号：USRE36061E

公开(公告)日：1999-01-26

申请号：US542360

申请日：1995-10-12

申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans Dieter Oberle

发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans Dieter Oberle

IPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C29/18 ,  G11C29/30 ,  G11C29/00

CPC分类号： G11C29/30 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/18

摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

摘要翻译： 集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。 内部加权电路各自分配给内部位线对中的相应一个。 外部一对位线通常被分配给内部位线。 分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。 位线解码器触发分离晶体管对。 提供外部加权电路。 鉴别器装置和预充电装置连接到外部位线对。 每对内部位线的内部位线彼此分开触发。 每对内部位线的内部位线彼此分开连接到外部位线对。