公开(公告)号：US08462538B2

公开(公告)日：2013-06-11

申请号：US13064180

申请日：2011-03-09

申请人： Shuichi Tsukada

发明人： Shuichi Tsukada

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C5/148 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/74

摘要： A semiconductor device includes a plurality of drain lines each being commonly connected to first nodes of a plurality of memory cells, a plurality of bit lines respectively connected to second nodes of the memory cells, a source line, a transistor that connects the drain lines to the source line, and a transistor that connects the source line to a ground potential in response to an access to the memory cell. Under control in which the memory cells are all deactivated, the semiconductor device controls the drain line to a drain potential that is higher than the ground potential, and controls the source line to be in a floating state by deactivating the transistors.

摘要翻译： 半导体器件包括多个漏极线，每条漏极线共同连接到多个存储单元的第一节点，分别连接到存储器单元的第二节点的多个位线，源极线，将漏极线连接到 源极线以及响应于对存储器单元的访问而将源极线连接到地电位的晶体管。 在其中存储器单元全部被去激活的控制下，半导体器件将漏极线控制到高于接地电位的漏极电位，并且通过停用晶体管来将源极线控制为浮置状态。

公开(公告)号：US08223536B2

公开(公告)日：2012-07-17

申请号：US12882803

申请日：2010-09-15

申请人： Yasuko Tonomura ,  Shuichi Tsukada

发明人： Yasuko Tonomura ,  Shuichi Tsukada

IPC分类号： G11C11/00

CPC分类号： G11C5/08 ,  G11C5/145 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069

摘要： A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.

摘要翻译： 半导体存储器件包括：相变元件（RP）和存储单元晶体管（MN0），其控制相对于相变元件（RP）的数据的写入和读取; 存储单元晶体管（MN0）在第一（读​​）操作模式中基于第一电位（VPS）向相变元件（RP）提供电流，并且在第二（写）操作模式中，基于 第一电位（VPS），并随后提供基于高于第一电位（VPS）的第二电位（VPP）的电流。 在写入操作中，消耗电流降低。

公开(公告)号：US08054679B2

公开(公告)日：2011-11-08

申请号：US12213195

申请日：2008-06-16

申请人： Kiyoshi Nakai ,  Shuichi Tsukada ,  Yusuke Jono

发明人： Kiyoshi Nakai ,  Shuichi Tsukada ,  Yusuke Jono

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.

摘要翻译： 相变存储器件包括：相变元件，用于通过改变电阻状态来重写地存储数据; 存储单元，布置在字线和位线的交点处，并由所述相变元件和串联连接的二极管形成; 形成在存储单元下方的扩散层中的选择晶体管，用于响应于连接到栅极的字线的电位选择性地控制二极管的阳极与地线之间的电连接; 以及预充电电路，用于将对应于未选择字线的存储单元下面的扩散层预充电到预定电压，并且用于将与所选择的字线相对应的存储单元下面的扩散层与预定电压断开。

公开(公告)号：US20110063890A1

公开(公告)日：2011-03-17

申请号：US12882803

申请日：2010-09-15

申请人： Yasuko Tonomura ,  Shuichi Tsukada

发明人： Yasuko Tonomura ,  Shuichi Tsukada

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C5/08 ,  G11C5/145 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069

摘要： A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.

摘要翻译： 半导体存储器件包括：相变元件（RP）和存储单元晶体管（MN0），其控制相对于相变元件（RP）的数据的写入和读取; 存储单元晶体管（MN0）在第一（读​​）操作模式中基于第一电位（VPS）向相变元件（RP）提供电流，并且在第二（写）操作模式中，基于 第一电位（VPS），并随后提供基于高于第一电位（VPS）的第二电位（VPP）的电流。 在写入操作中，消耗电流降低。

公开(公告)号：US07719296B2

公开(公告)日：2010-05-18

申请号：US11819273

申请日：2007-06-26

申请人： Takashi Amemiya ,  Shuichi Tsukada

发明人： Takashi Amemiya ,  Shuichi Tsukada

IPC分类号： G01R31/02 ,  H01R12/00

CPC分类号： H01R13/2464 ,  G01R1/07314 ,  G01R1/0735 ,  H01R2201/20

摘要： In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them.

摘要翻译： 在本发明中，在探针卡的电路基板的下表面侧安装有检查接触结构。 在检查接触结构中，具有突出导电部分的弹性片分别安装在硅树脂基底的两个表面上。 硅基板在垂直方向上形成有通过其的通电路径，并且片状导电部分从上方和下方与导流路径接触。 上侧的导电部与电路基板的连接端子接触。 在检查晶片的电性的时候，晶片上的电极焊盘被压在下侧的导电部分上，从而与它们接触。

公开(公告)号：US20080159034A1

公开(公告)日：2008-07-03

申请号：US12073017

申请日：2008-02-28

申请人： Shuichi Tsukada

发明人： Shuichi Tsukada

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065

摘要： A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when overdriving begins, and is designed to supply voltage of power supply VDD1 to parallel-connected sense amplifiers. Capacitor C1 accumulates electrical charges referenced to in association with electrical charges supplied to sense the amplifiers via MOS transistor TP1. MOS transistor TP2 is turned on when overdriving begins, to supply voltage of power supply VDD1 to capacitor C1. The control circuit controls so that MOS transistors TP1, TP2 are turned off when the capacitor potential has reached voltage VREF1. There is also provided a MOS transistor turned on after the MOS transistors TP1, TP2 are turned off to supply a power supply voltage equal to the voltage VREF1 to the plural sense amplifiers.

摘要翻译： 可以在不提供准确的延迟时间的情况下提供DRAM中的过驱动周期的系统。 设置有MOS晶体管TP1，电容器C1，MOS晶体管TP2以及控制电路。 MOS晶体管TP 1在过驱动开始时导通，并被设计为将电源VDD1的电压提供给并联连接的读出放大器。 电容器C 1以与提供的电荷相关联的电荷积累电荷，以经由MOS晶体管TP 1感测放大器。 MOS晶体管TP2在过驱动时导通，将电源VDD1的电压提供给电容器C1。 控制电路进行控制，使得MOS晶体管TP1，TP2在电容器电位达到电压VREF 1时截止。 在MOS晶体管TP1，TP2截止之后还提供一个MOS晶体管导通，以向多个读出放大器提供等于电压VREF 1的电源电压。

公开(公告)号：US07106641B2

公开(公告)日：2006-09-12

申请号：US11064837

申请日：2005-02-25

申请人： Shuichi Tsukada

发明人： Shuichi Tsukada

IPC分类号： G11C29/30

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C11/4094 ,  G11C29/83 ,  G11C2207/2227

摘要： To provide a dynamic semiconductor memory device wherein it is possible to perform a reliable redundancy relief with a small layout area and high redundancy relieving rate while properly dealing with the standby current fault caused by a short-circuit defect between a bit line and word line. A common current-limiting element is provided for an equalizer circuit for a bit line pair on one side and another equalizer circuit for another bit line pair on the other side in a shared sense amplifier, and a bit line precharge potential is supplied to the equalizer circuits on the both sides through the current-limiting element.

摘要翻译： 提供一种动态半导体存储器件，其中可以在正确处理由位线和字线之间的短路缺陷引起的待机电流故障的同时，以小的布局面积和高的冗余缓解率执行可靠的冗余度。 一个公共限流元件用于位于一侧的位线对的均衡器电路和用于共享读出放大器另一侧的另一个位线对的另一个均衡器电路，位线预充电电位被提供给均衡器 两侧的电路通过限流元件。

公开(公告)号：US4657058A

公开(公告)日：1987-04-14

申请号：US726700

申请日：1985-04-24

申请人： Kazuyuki Kabe ,  Tuneo Morikawa ,  Shuichi Tsukada

发明人： Kazuyuki Kabe ,  Tuneo Morikawa ,  Shuichi Tsukada

IPC分类号： B60C9/20 ,  B60C9/00 ,  B60C9/08 ,  D02G3/48

CPC分类号： B60C9/0042 ,  B60C9/08

摘要： A pneumatic tire of which the durability of the turnup portions of a carcass layer is greatly improved. The tire consists of left and right bead portions, left and right side wall portions continuing from the bead portions, a tread positioned between the side wall portions, a carcass layer provided between the left and right bead portions so that a cord angle with respect to the circumferential direction the tire is 70.degree.-90.degree., and a belt reinforcement layer provided between the tread and carcass layer, characterized in that the carcass layer is formed by burying 20-60 aromatic polyamide fiber cords of 0.55-0.65 mm in diameter per 5 cm of the carcass layer in an equatorial plane in the tire in rubber coats of which a 100% modulus is 30-70 kg/cm.sup.2.

摘要翻译： 一种充气轮胎，其胎体层的翻转部的耐久性大大提高。 轮胎由左右胎圈部分，从胎边部分延伸的左右侧壁部分，位于侧壁部分之间的胎面，设置在左右胎圈部分之间的胎体层，使得帘线相对于 轮胎为70°-90°的圆周方向，以及设置在胎面和胎体层之间的带束加强层，其特征在于，通过将20-60个直径为0.55-0.65mm的芳族聚酰胺纤维帘线埋入，形成胎体层 5厘米的胎体层在轮胎中的赤道平面上，其橡胶涂层的100％模量为30-70kg / cm 2。

公开(公告)号：US08879312B2

公开(公告)日：2014-11-04

申请号：US14201999

申请日：2014-03-10

申请人： Shuichi Tsukada

发明人： Shuichi Tsukada

IPC分类号： G11C11/00 ,  H02M3/07 ,  G11C5/14 ,  G11C13/00 ,  H02M1/00

CPC分类号： G11C13/0069 ,  G11C5/145 ,  G11C13/0004 ,  G11C13/0038 ,  H02M3/073 ,  H02M2001/007 ,  H02M2001/009

摘要： A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.

摘要翻译： 电源电压产生电路包括产生第一内部电源电压的第一电荷泵电路和产生第二内部电源电压的第二电荷泵电路。 第二内部电源电压的绝对值大于第一内部电源电压的绝对值。 第一电荷泵电路的输出端子连接到第二电荷泵电路的次级侧充电端子。 次级侧是对应的电荷泵电路的输出侧，充电端子是向相应的电荷泵电路的次级侧输出端子提供辅助电荷的辅助充电端子。 第二电荷泵电路的输出端子输出作为向充电端子施加的第一内部电源电压的值加上规定的电压值的结果的电压值。

公开(公告)号：US08737124B2

公开(公告)日：2014-05-27

申请号：US13457262

申请日：2012-04-26

申请人： Shuichi Tsukada ,  Yasuhiro Uchiyama

发明人： Shuichi Tsukada ,  Yasuhiro Uchiyama

IPC分类号： G11C11/24 ,  H01L27/06 ,  H01L27/102 ,  G11C11/39 ,  H01L49/02 ,  H01L29/78

CPC分类号： G11C11/39 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/411 ,  H01L27/075 ,  H01L27/1021 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/7841

摘要： There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third region that forms a PN junction with the second region. The capacitor includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.

摘要翻译： 提供了包括字线，位线，电源节点，存储元件和电容器的半导体器件。 存储器元件至少包括在位线和电源节点之间形成PN结的第一和第二区域，以及与第二区域形成PN结的第三区域。 电容器包括独立于存储元件的第二区域设置并电连接到存储元件的第二区域的第一电极和连接到字线的第二电极。