公开(公告)号：US20220392895A1

公开(公告)日：2022-12-08

申请号：US17653020

申请日：2022-03-01

申请人： Georgia Tech Research Corporation

发明人： Elaine Rhoades ,  Aaron S. Green ,  William Daniel Hunt

IPC分类号： H01L27/08 ,  G05F1/565 ,  H01L27/095

摘要： An exemplary embodiment of the present disclosure provides a detector configured to output a signal associated with one or more interactions with subatomic particles. The detector comprises a sensor comprising a first diode comprising first semiconductor material abutting a first metal and forming a first junction, wherein the sensor is configured to be exposed to subatomic particles and a voltage reference member configured to generate a reference measurement. The sensor and the voltage reference member form a bandgap reference circuit. The present disclosure also provides methods for detecting subatomic particles from a solid-state detector comprising a first Schottky diode in electrical communication with a reference voltage member comprising a parallel circuit of two or more second Schottky diodes, wherein the first Schottky diode is configured to be exposed to subatomic particles and the second Schottky diodes of the reference voltage member are configured to generate a reference measurement.

公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC分类号： H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

摘要： Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US10770577B2

公开(公告)日：2020-09-08

申请号：US16250367

申请日：2019-01-17

申请人： DENSO CORPORATION

发明人： Toshinori Maruyama

IPC分类号： H01L29/78 ,  H01L27/07 ,  H01L29/866 ,  H01L27/02 ,  H01L27/095 ,  H01L29/872 ,  H02K11/04 ,  H02K19/36 ,  H02M1/08 ,  H02K9/06

摘要： A rectifier has a rectification circuit configured to rectify multi-phase alternating current generated by a rotating electric machine into direct current. The rectifier includes upper-arm semiconductor switching elements included in an upper arm of the rectification circuit, upper-arm protection diodes included in the upper arm and each being electrically connected in parallel with one of the upper-arm semiconductor switching elements, lower-arm semiconductor switching elements included in a lower arm of the rectification circuit, and lower-arm protection diodes included in the lower arm and each being electrically connected in parallel with one of the lower-arm semiconductor switching elements. Each of the upper-arm and lower-arm protection diodes is configured to have, when a reverse voltage higher than a breakdown voltage of the protection diode is applied to the protection diode, an operating resistance that is higher than three times an operating resistance of any of the upper-arm and lower-arm semiconductor switching elements.

公开(公告)号：US20200185543A1

公开(公告)日：2020-06-11

申请号：US16789499

申请日：2020-02-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Jefferson W. HALL

IPC分类号： H01L29/872 ,  H01L29/06 ,  H01L29/47 ,  H01L27/07 ,  H01L27/095 ,  H01L29/66 ,  H01L27/02

摘要： A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.

公开(公告)号：US20190288125A1

公开(公告)日：2019-09-19

申请号：US15919475

申请日：2018-03-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Jefferson W. HALL

IPC分类号： H01L29/872 ,  H01L27/02 ,  H01L27/07 ,  H01L27/095 ,  H01L29/66

摘要： A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.

公开(公告)号：US20190288123A1

公开(公告)日：2019-09-19

申请号：US16353548

申请日：2019-03-14

申请人： EMBERION OY

发明人： Sami KALLIOINEN ,  Helena POHJONEN

IPC分类号： H01L29/812 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10 ,  H01L27/095 ,  H01L27/146 ,  H01L29/66 ,  H01L29/40

摘要： A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.

公开(公告)号：US10381489B2

公开(公告)日：2019-08-13

申请号：US15764426

申请日：2016-09-27

申请人： NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY ,  JAPAN SCIENCE AND TECHNOLOGY AGENCY

发明人： Takashi Fukui ,  Katsuhiro Tomioka

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L27/095 ,  H01L29/808 ,  H01L29/812 ,  H01L29/06 ,  H01L29/04 ,  H01L29/205

摘要： The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.

公开(公告)号：US20190237574A1

公开(公告)日：2019-08-01

申请号：US16250367

申请日：2019-01-17

申请人： DENSO CORPORATION

发明人： Toshinori MARUYAMA

IPC分类号： H01L29/78 ,  H02M1/08 ,  H02K19/36 ,  H02K11/04 ,  H01L27/02 ,  H01L27/095 ,  H01L29/872

摘要： A rectifier has a rectification circuit configured to rectify multi-phase alternating current generated by a rotating electric machine into direct current. The rectifier includes upper-arm semiconductor switching elements included in an upper arm of the rectification circuit, upper-arm protection diodes included in the upper arm and each being electrically connected in parallel with one of the upper-arm semiconductor switching elements, lower-arm semiconductor switching elements included in a lower arm of the rectification circuit, and lower-arm protection diodes included in the lower arm and each being electrically connected in parallel with one of the lower-arm semiconductor switching elements. Each of the upper-arm and lower-arm protection diodes is configured to have, when a reverse voltage higher than a breakdown voltage of the protection diode is applied to the protection diode, an operating resistance that is higher than three times an operating resistance of any of the upper-arm and lower-arm semiconductor switching elements.

公开(公告)号：US20190051649A1

公开(公告)日：2019-02-14

申请号：US16161956

申请日：2018-10-16

申请人： SONY CORPORATION

发明人： MASAHIRO MITSUNAGA

IPC分类号： H01L27/095 ,  H01L41/25 ,  H01L41/08 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/10 ,  H01L29/66 ,  H01L21/28 ,  H01L29/205

摘要： A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

公开(公告)号：US20180374943A1

公开(公告)日：2018-12-27

申请号：US15628932

申请日：2017-06-21

申请人： Cree, Inc.

发明人： Yueying Liu ,  Saptharishi Sriram ,  Scott Sheppard

IPC分类号： H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/20 ,  H01L27/095 ,  H01L21/8252 ,  H01L29/66 ,  H01L21/326 ,  H01L29/205

摘要： A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.