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公开(公告)号:US12101188B2
公开(公告)日:2024-09-24
申请号:US17834141
申请日:2022-06-07
申请人: TQ DELTA, LLC
发明人: Marcos C. Tzannes
IPC分类号: H04L1/18 , H03M13/00 , H03M13/09 , H03M13/27 , H04L1/00 , H04L1/08 , H04L1/1607 , H04L1/1809 , H04L1/1829 , H04L1/1867 , H04L12/00 , H04L12/54 , H04L45/00 , H04L47/10 , H04L47/2425 , H04L47/2441 , H04L47/32 , H04L49/552 , H04L69/324 , H04L12/70
CPC分类号: H04L1/18 , H03M13/00 , H03M13/09 , H03M13/091 , H03M13/2707 , H03M13/6513 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/08 , H04L1/1607 , H04L1/1809 , H04L1/1835 , H04L1/1874 , H04L12/5601 , H04L45/00 , H04L45/72 , H04L47/10 , H04L47/2433 , H04L47/2441 , H04L47/32 , H04L49/552 , H04L69/324 , H04L2012/5647
摘要: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.
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公开(公告)号:US12081333B2
公开(公告)日:2024-09-03
申请号:US18073974
申请日:2022-12-02
发明人: Jian Li , Changlong Xu , Chao Wei , Jilei Hou
CPC分类号: H04L1/0071 , H03M13/13 , H03M13/2707 , H03M13/2742 , H03M13/2757 , H03M13/296 , H04L1/0057 , H04L1/0058 , H04L1/0061
摘要: Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.
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公开(公告)号:US12081240B2
公开(公告)日:2024-09-03
申请号:US18286009
申请日:2022-04-13
申请人: MARIS—TECH LTD
发明人: Magenya Roshanski
CPC分类号: H03M13/35 , H04L1/0086 , H03M13/27 , H03M13/353 , H03M13/6547 , H04L65/762
摘要: A method and apparatus for transmitting a streaming media with Forward Error Correction (FEC). Upon receiving the streaming media, the technique includes: encoding, segmenting and packeting frames comprised therein to generate a packetized elementary stream of media packets with variable sizes; for each L sequential media packets, calculating a “random loss” (RL) FEC parity and generating a respective RL FEC packet associated therewith; calculating “burst loss” (BL) FEC parities in accordance with a predefined FEC scheme and generating respective BL FEC structures bearing FEC headers and usable for generating BL FEC packets; calculating size-related parameters of a group of sequential media packets, the group being selected in accordance with the FEC scheme; and, transmitting the packetized elementary stream with interleaved FEC packets. The BL FEC packets are transmitted merely when the calculated size-related parameters meet a size-related burst loss (SRB) criterion defined by the FEC scheme.
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公开(公告)号:US20240283592A1
公开(公告)日:2024-08-22
申请号:US18586414
申请日:2024-02-23
发明人: Jong Ee OH , Min Ho CHEONG , Sok Kyu LEE
IPC分类号: H04L5/00 , H03M13/11 , H03M13/23 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H04B7/04 , H04B7/06 , H04B7/08 , H04L1/00 , H04L1/06 , H04L27/18 , H04L27/26 , H04L27/34
CPC分类号: H04L5/0046 , H03M13/256 , H03M13/271 , H03M13/356 , H04B7/04 , H04B7/0697 , H04B7/08 , H04L1/0041 , H04L1/0057 , H04L1/06 , H04L1/0618 , H04L5/0026 , H04L27/186 , H04L27/2627 , H04L27/3416 , H03M13/1102 , H03M13/23 , H03M13/2957
摘要: Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.
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公开(公告)号:US12068756B2
公开(公告)日:2024-08-20
申请号:US18325364
申请日:2023-05-30
发明人: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC分类号: H03M13/1102 , H03M13/116 , H03M13/2778 , H03M13/2903 , H03M13/618 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/2906
摘要: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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公开(公告)号:US20240259035A1
公开(公告)日:2024-08-01
申请号:US18629536
申请日:2024-04-08
申请人: ZTE Corporation
发明人: Mengzhu Chen , Jin Xu , Jun Xu
CPC分类号: H03M13/635 , H03M13/13 , H03M13/2792
摘要: Provided is a rate matching method and device for a Polar code. The method includes: concatenating K information bits and (N−K) frozen bits to generate a bit sequence of N bits, and encoding the bit sequence of N bits by means of a Polar code encoder with a generator matrix of size N×N to generate an initial bit sequence {S0, S1, . . . , SN−1} of N bits, where K and N are both positive integers and K is less than or equal to N; dividing a circular buffer into q parts, selecting bits from the initial bit sequence {S0, S1, . . . , SN−1} in a non-repeated manner, and writing the bits into the q parts of the circular buffer according to a predefined rule, where q=1, 2, 3 or 4; and sequentially selecting a bit sequence of a specified length from a predefined starting position in a bit sequence in the circular buffer and taking the bit sequence of the specified length as a bit sequence to be transmitted.
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公开(公告)号:US12052036B2
公开(公告)日:2024-07-30
申请号:US18140164
申请日:2023-04-27
发明人: Mihail Petrov
CPC分类号: H03M13/2792 , H03M13/116 , H03M13/1165 , H03M13/1168 , H03M13/255 , H03M13/27 , H03M13/2707 , H03M13/271 , H03M13/2778 , H03M13/2957 , H03M13/356 , H03M13/6325 , H03M13/6552 , H03M13/6555 , H04L1/0058 , H04L1/0606 , H04L1/0618
摘要: A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×M′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×M′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.
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公开(公告)号:US12028159B2
公开(公告)日:2024-07-02
申请号:US18143394
申请日:2023-05-04
发明人: Chunxuan Ye , Fengjun Xi , Sungkwon Hong , Kyle Jung-Lin Pan , Robert L. Olesen
CPC分类号: H04L1/0071 , H03M13/05 , H03M13/13 , H03M13/27 , H03M13/2778 , H03M13/2792 , H03M13/2906 , H03M13/618 , H03M13/6306 , H03M13/6356 , H03M13/6362 , H03M13/6368 , H04L1/0041 , H04L1/0057 , H04L1/0067
摘要: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.
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公开(公告)号:US20240204804A1
公开(公告)日:2024-06-20
申请号:US18522242
申请日:2023-11-29
发明人: Yu-Chih Huang , Li-Yang Tseng
CPC分类号: H03M13/27 , H03M13/6577 , H04L1/0041 , H04L1/0045 , H04L1/0071
摘要: A data processing method for a DNN model includes: reading weights of transmission data; quantizing each weight into bits sequentially including first, second, third, and fourth-type bits; sequentially interleaving the first-type bit into a first bit set; sequentially interleaving each second-type bit into second bit sets and reading a second compression rate of each second bit set in response to the compressible second bit sets; interleaving the third-type bit into a third bit set and reading a third compression rate of the third bit set in response to the compressible third bit set; compressing each second bit set with the second compression rate, and compressing the third bit set with the third compression rate; sequentially coding the first bit set, each compressed second bit set, and the compressed third bit set to generate first encoded data corresponding to the transmission data; transmitting the first encoded data to an external device.
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公开(公告)号:US12009837B2
公开(公告)日:2024-06-11
申请号:US18330669
申请日:2023-06-07
申请人: Kioxia Corporation
发明人: Hironori Uchikawa
CPC分类号: H03M13/159 , H03M13/098 , H03M13/1177 , H03M13/1575 , H03M13/2732 , H03M13/2735
摘要: A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.
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