公开(公告)号：WO2017099770A1

公开(公告)日：2017-06-15

申请号：PCT/US2015/064844

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： CLENDENNING, Scott B. ,  THEN, Han Wui ,  PLOMBON, John J. ,  MCSWINEY, Michael L.

IPC: H01L21/20 ,  H01L21/70

CPC classification number: H01L21/28088 ,  C23C16/30 ,  H01L21/28556 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/4966

Abstract: Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了具有钌磷薄膜的半导体器件并且进一步描述了沉积薄膜的工艺。 薄膜可以沉积在晶体管器件的栅极叠层中或互连结构中。 沉积膜的过程可以包括化学气相沉积并且可以包括钌前体。 前体可能含有磷。 在沉积期间可以使用共反应物。 共反应物可以包括磷基化合物。 栅极材料可以在栅极堆叠中沉积在膜上。 钌磷膜可以是金属扩散阻挡层和粘附层，并且对于一些实施例，该膜可以是功函数金属。 其他实施例可以被描述和/或要求保护。

公开(公告)号：WO2017079512A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/060454

申请日：2016-11-04

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： BI, Xiaochuan ,  KRAKOWSKI, Tracey, L. ,  BANERJEE, Suman

IPC: H01L27/06 ,  H01L21/70 ,  H01L29/864

CPC classification number: H01L29/864 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/66159 ,  H01L29/66575 ,  H01L29/7371 ,  H01L29/7378 ,  H01L29/7848 ,  H01L2223/6683

Abstract: In described examples, a vertically oriented BARITT diode (108) is formed in an integrated circuit (100). The BARITT diode (108) has a source (126) proximate to a top surface of a substrate (102) of the integrated circuit (100), a drift region (128) immediately below the source (126) in semiconductor material of the substrate (102), and a collector (130) in the semiconductor material of the substrate (102) immediately below the drift region (128). A dielectric isolation structure (132) laterally surrounds the drift region (128), extending from the source (126) to the collector (130). The source (126) may optionally include a silicon germanium layer or may optionally include a Schottky barrier contact.

Abstract translation: 在所描述的示例中，在集成电路（100）中形成垂直取向BARITT二极管（108）。 BARITT二极管（108）具有靠近集成电路（100）的衬底（102）的顶表面的源极（126），在衬底的半导体材料中的源极（126）正下方的漂移区域（128） （102）以及位于漂移区（128）正下方的衬底（102）的半导体材料中的集电极（130）。 介电隔离结构（132）横向围绕漂移区（128），从源极（126）延伸到集电极（130）。 源（126）可以可选地包括硅锗层或者可以可选地包括肖特基势垒接触。

公开(公告)号：WO2016070274A1

公开(公告)日：2016-05-12

申请号：PCT/CA2015/051134

申请日：2015-11-04

Applicant: SOLANTRO SEMICONDUCTOR CORP.

Inventor： ORR, Raymond Kenneth ,  BACQUE, James Benson ,  HARRIS, Mark Roy

IPC: H01L21/70 ,  H01F17/00 ,  H01L23/48 ,  H01L23/64 ,  H01L27/00 ,  H05K3/30

CPC classification number: H01F27/2804 ,  H01F27/2852 ,  H01F27/29 ,  H01F27/303 ,  H01F2027/2819 ,  H01L21/4842 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49544 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48177 ,  H01L2924/00014 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/173 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45099

Abstract: The present disclosure relates to non-planar inductive electrical elements in semiconductor package lead frames. A non-planar inductive element is formed from a lead frame in a semiconductor package. The semiconductor package also includes at least one semiconductor die coupled to the lead frame. The non-planar inductive element could be formed by deforming portions of a patterned planar lead frame blank to form the non-planar inductive element in a deformed lead frame blank. The deformed lead frame blank and the at least one semiconductor die could then be packaged into a semiconductor package. A setting tool could be used to deform the lead frame blank. A configurable lead frame blank could be configurable into any of a variety of inductive elements, through interconnection of lead frame segments using wire bonds, for example.

Abstract translation: 本公开涉及半导体封装引线框架中的非平面感应电元件。 非平面感应元件由半导体封装中的引线框形成。 半导体封装还包括耦合到引线框架的至少一个半导体管芯。 可以通过使图案化的平面引线框架坯件的部分变形以在变形的引线框架坯件中形成非平面感应元件来形成非平面感应元件。 然后可以将变形的引线框架坯件和至少一个半导体管芯封装成半导体封装。 可以使用设置工具使引线框架空白变形。 例如，通过使用引线键的引线框架段的互连，可配置的引线框架空白可以被配置成各种电感元件中的任何一个。

公开(公告)号：WO2012150977A1

公开(公告)日：2012-11-08

申请号：PCT/US2012/026199

申请日：2012-02-22

Applicant: GILBARCO. S.R.I. ,  GILBARCO INC. ,  BROGI, Graziano

Inventor： BROGI, Graziano

IPC: B60S5/02 ,  H01L21/70 ,  G06F3/14 ,  G06K7/00

CPC classification number: G06F3/044 ,  G06F2203/04103

Abstract: A fuel dispenser comprising a touchpad that includes a capacitive sensor made from diffusing indium tin oxide on a transparent plastic support and laminated between two panes of glass, a display adjacent to one of the glass panes, and circuitry operatively connected to the sensor and the display. The touchpad is configured to output data representative of any capacitive coupling effects detected by the sensor.

Abstract translation: 一种燃料分配器，包括触摸板，其包括电容式传感器，所述电容式传感器由透明塑料支架上的氧化铟锡扩散器制成，并且层压在两个玻璃板之间，与所述玻璃板之一相邻的显示器以及可操作地连接到所述传感器和所述显示器 。 触摸板被配置为输出表示由传感器检测到的任何电容耦合效应的数据。

公开(公告)号：WO2010141610A1

公开(公告)日：2010-12-09

申请号：PCT/US2010/037101

申请日：2010-06-02

Applicant: ARIZONA BOARD OF REGENTS ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY ,  TAO, Nongjian ,  FORZANI, Erica ,  IGLESIAS, Rodrigo

Inventor： TAO, Nongjian ,  FORZANI, Erica ,  IGLESIAS, Rodrigo

IPC: G01N27/30 ,  H01L21/70

CPC classification number: G01N27/27 ,  G01N21/05 ,  G01N21/783 ,  G01N31/223 ,  G01N33/0037 ,  Y02A50/245 ,  Y10T436/173845

Abstract: A gas-phase detection system based on detecting optochemical and optoelectrochemical signals. The sensing platform is particularly powerful for detection of nitrogen oxides at low ppbV concentrations. The optochemical analysis is based on the color development due to a chemical reaction taking place in an optimized material. The electrochemical analysis can be based on the doping level or redox potential changes of an electrochemical sensor; and optoelectrochemical detection can be based on a combination of the electrochemical and optoelectrochemical methodologies. Each independent signal can be simultaneously detected, increasing the reliability of detection.

Abstract translation: 一种基于光电化学和光电信号检测的气相检测系统。 传感平台对于检测低ppbV浓度的氮氧化物特别强大。 光化学分析是由于化学反应发生在优化材料中的颜色发展。 电化学分析可以基于电化学传感器的掺杂水平或氧化还原电位变化; 光电化学检测可以基于电化学和光电化学方法的组合。 可以同时检测每个独立信号，提高检测的可靠性。

公开(公告)号：WO2010080988A3

公开(公告)日：2010-09-10

申请号：PCT/US2010020485

申请日：2010-01-08

Applicant: APPLE INC ,  CHANG SHIH CHANG ,  ZHONG JOHN Z ,  HUANG LILI ,  HONG SEUNG JAE ,  YOUNGS LYNN

Inventor： CHANG SHIH CHANG ,  ZHONG JOHN Z ,  HUANG LILI ,  HONG SEUNG JAE ,  YOUNGS LYNN

IPC: H01L21/70 ,  G06F3/041 ,  G06F3/044

CPC classification number: G06F3/0416 ,  G06F3/044 ,  H05K1/0306 ,  H05K3/0097 ,  H05K2201/0317 ,  H05K2201/0326 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for fabricating thin DITO or SITO touch sensor panels with a thickness less than a minimum thickness tolerance of existing manufacturing equipment. In one embodiment, a sandwich of two thin glass sheets is formed such that the combined thickness of the glass sheets does not drop below the minimum thickness tolerance of existing manufacturing equipment when thin film process is performed on the surfaces of the sandwich during fabrication. The sandwich may eventually be separated to form two thin SITO/DITO panels. In another embodiment, the fabrication process involves laminating two patterned thick substrates, each having at least the minimum thickness tolerance of existing manufacturing equipment. One or both of the sides of the laminated substrates are then thinned so that when the substrates are separated, each is a thin DITO/SITO panel having a thickness less than the minimum thickness tolerance of existing manufacturing equipment.

Abstract translation: 一种制造厚度小于现有制造设备的最小厚度公差的薄DITO或SITO触摸传感器面板的方法。 在一个实施例中，形成两个薄玻璃片的夹层，使得当在制造期间在夹层的表面上执行薄膜工艺时，玻璃片的组合厚度不会降低到现有制造设备的最小厚度公差之下。 三明治可能最终会分开形成两个薄的SITO / DITO面板。 在另一个实施例中，制造工艺涉及层压两个图案化的厚基底，每个基底至少具有现有制造设备的最小厚度公差。 然后，薄片化一个或两个层压衬底的侧面，从而当衬底分离时，每个都是厚度小于现有制造设备的最小厚度公差的薄DITO / SITO面板。

公开(公告)号：WO2010080988A2

公开(公告)日：2010-07-15

申请号：PCT/US2010/020485

申请日：2010-01-08

Applicant: APPLE INC. ,  CHANG, Shih, Chang ,  ZHONG, John, Z. ,  HUANG, Lili ,  HONG, Seung, Jae ,  YOUNGS, Lynn

Inventor： CHANG, Shih, Chang ,  ZHONG, John, Z. ,  HUANG, Lili ,  HONG, Seung, Jae ,  YOUNGS, Lynn

IPC: H01L21/70 ,  G06F3/041 ,  G06F3/044

CPC classification number: G06F3/0416 ,  G06F3/044 ,  H05K1/0306 ,  H05K3/0097 ,  H05K2201/0317 ,  H05K2201/0326 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for fabricating thin DITO or SITO touch sensor panels with a thickness less than a minimum thickness tolerance of existing manufacturing equipment. In one embodiment, a sandwich of two thin glass sheets is formed such that the combined thickness of the glass sheets does not drop below the minimum thickness tolerance of existing manufacturing equipment when thin film process is performed on the surfaces of the sandwich during fabrication. The sandwich may eventually be separated to form two thin SITO/DITO panels. In another embodiment, the fabrication process involves laminating two patterned thick substrates, each having at least the minimum thickness tolerance of existing manufacturing equipment. One or both of the sides of the laminated substrates are then thinned so that when the substrates are separated, each is a thin DITO/SITO panel having a thickness less than the minimum thickness tolerance of existing manufacturing equipment.

Abstract translation: 用于制造厚度小于现有制造设备的最小厚度公差的薄DITO或SITO触摸传感器面板的方法。 在一个实施例中，形成两个薄玻璃板的夹层，使得当在制造期间在夹层的表面上执行薄膜处理时，玻璃板的组合厚度不会下降到现有制造设备的最小厚度公差之下。 三明治可能最终分开形成两个薄的SITO / DITO面板。 在另一个实施例中，制造工艺包括层压两个图案化的厚基板，每个基板至少具有现有制造设备的最小厚度公差。 然后层压基板的一个或两个侧面变薄，使得当基板分离时，每个是具有小于现有制造设备的最小厚度公差的厚度的薄DITO / SITO面板。

公开(公告)号：WO2009058187A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/011463

申请日：2008-10-02

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： BULUCEA, Constantin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/70 ,  H01L21/8238

CPC classification number: H01L29/7833 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, 480, 500, 510, 530, or 540) has a hypoabrupt vertical dopant profile below one (104, 264, or 564) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108, 268, or 568). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120, 280, or 580) situated along the other source/drain zone (102, 262, or 562). The combination of the hypoabrupt vertical dopant profile below the first- mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second- mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380,480,500,610） ，530或540）具有低于其源极/漏极区的一个（104,264或564）的低破坏垂直掺杂剂轮廓，用于减小沿着该源极/漏极区与相邻主体材料（108， 268或568）。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍，不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102,262或562）设置的更重掺杂的凹穴部分（120,280或580）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物轮廓的组合以及通常用作源的第二提及的源极/漏极区的凹穴部分的组合使得所得到的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：WO2009020678A3

公开(公告)日：2009-04-02

申请号：PCT/US2008062277

申请日：2008-05-01

Applicant: UNIV CALIFORNIA ,  MISHRA UMESH KUMAR ,  MCCARTHY LEE S

Inventor： MISHRA UMESH KUMAR ,  MCCARTHY LEE S

IPC: H01L21/70

CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7371 ,  H01L29/7786 ,  H01L29/7802

Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III -nitride semiconductor, at a temperature below 550 0C, to form a device quality heterojunction between the first semiconductor material and the Ill-nitride semiconductor, wherein the first semiconductor material is different from the Ill-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the Ill-nitride semiconductor.

Abstract translation: 一种制造电子器件的方法，包括在低于550℃的温度下将第一半导体材料晶片键合到III族氮化物半导体，以在第一半导体材料和III族氮化物半导体之间形成器件质量异质结，其中第一 半导体材料不同于III族氮化物半导体，并且与III族氮化物半导体相比，针对优异的性质或在注入区中的优选的集成或制造特性来选择半导体材料。

公开(公告)号：WO2008060530A1

公开(公告)日：2008-05-22

申请号：PCT/US2007/023827

申请日：2007-11-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  HU, Evelyn, L. ,  NAKAMURA, Shuji ,  CHOI, Yong, Seok ,  SHARMA, Rajat ,  WANG, Chio-Fu

Inventor： HU, Evelyn, L. ,  NAKAMURA, Shuji ,  CHOI, Yong, Seok ,  SHARMA, Rajat ,  WANG, Chio-Fu

IPC: H01L21/70 ,  H01L23/52

CPC classification number: H01L33/10 ,  H01L33/0075 ,  H01L33/0095

Abstract: A method for ensuring the structural integrity of III-nitride opto-electronic or opto-mechanical air-gap nano-structured devices, comprising (a) performing ion beam implantation in a region of the III-nitride opto-electronic and opto-mechanical air-gap nano-structured device and (b) performing a bandgap selective photo-electro-chemical (PEC) etch on the III-nitride opto-electronic and opto-mechanical air-gap nano-structured device. The method also comprises the suitable design of distributed Bragg reflector (DBR) structures for the PEC etching and the ion-beam treatment, the suitable design of photonic crystal distributed Bragg reflector (PCDBR) structures for PEC etching and the ion-beam treatment, the suitable placement of protection layers to prevent the ion-beam damage to optical activity and PEC etch selectivity, and a suitable annealing treatment for curing the material quality after the ion-beam treatment.

Abstract translation: 一种用于确保III族氮化物光电子或光电机械气隙纳米结构器件的结构完整性的方法，包括（a）在III族氮化物光电子和光机电空气的区域中进行离子束注入 （b）在III族氮化物光电子和光机电气隙纳米结构器件上进行带隙选择性光电化学（PEC）蚀刻。 该方法还包括用于PEC蚀刻和离子束处理的分布式布拉格反射器（DBR）结构的合适设计，用于PEC蚀刻和离子束处理的光子晶体分布布拉格反射器（PCDBR）结构的合适设计， 保护层的适当放置以防止离子束损伤光学活性和PEC蚀刻选择性，以及适当的退火处理以在离子束处理后固化材料质量。