公开(公告)号：WO2012092038A3

公开(公告)日：2012-11-15

申请号：PCT/US2011066271

申请日：2011-12-20

申请人： INTEL CORP ,  MUKHERJEE NILOY ,  DEWEY GILBERT ,  RADOSAVLJEVIC MARKO ,  CHAU ROBERT S ,  METZ MATTHEW V

发明人： MUKHERJEE NILOY ,  DEWEY GILBERT ,  RADOSAVLJEVIC MARKO ,  CHAU ROBERT S ,  METZ MATTHEW V

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28575 ,  H01L29/66446

摘要： A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

摘要翻译： 通常使用通过在源极和漏极中使用III-V半导体夹层来降低n沟道晶体管的接触电阻的方法。 在这方面，引入一种器件，其包括具有源极区和漏极区的n型晶体管，与晶体管相邻的第一层间电介质层，穿过第一层间介质层到源极区的沟槽，以及导电源接触 沟槽，源极触点通过III-V半导体夹层与源极区分离。 还公开并要求保护其他实施例。

公开(公告)号：WO2010074964A2

公开(公告)日：2010-07-01

申请号：PCT/US2009/067182

申请日：2009-12-08

申请人： INTEL CORPORATION ,  MAJHI, Prashant ,  GOEL, Niti ,  KOVESHNIKOV, Sergei ,  TSAI, Wilman ,  RADOSAVLJEVIC, Marko ,  PILLARESITTY, Ravi ,  GARGINI, Paolo

发明人： MAJHI, Prashant ,  GOEL, Niti ,  KOVESHNIKOV, Sergei ,  TSAI, Wilman ,  RADOSAVLJEVIC, Marko ,  PILLARESITTY, Ravi ,  GARGINI, Paolo

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7783 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66462

摘要： A group III-V MOSFET includes metal source and drain regions that are in direct contact with the quantum well region. Such an apparatus comprises a substrate, a III-V quantum well layer formed on the substrate, a III-V barrier layer formed on the quantum well layer, a gate dielectric layer formed on the barrier layer, a gate electrode formed on the gate dielectric layer, a first metal sidewall liner formed adjacent to both the quantum well layer and the barrier layer, a second metal sidewall liner formed adjacent to both the quantum well layer and the barrier layer, a metal source region adjacent to the first metal sidewall liner, and a metal drain region adjacent to the second metal sidewall liner.

摘要翻译： III-V族MOSFET包括与量子阱区域直接接触的金属源极和漏极区域。 这种装置包括衬底，形成在衬底上的III-V量子阱层，形成在量子阱层上的III-V阻挡层，形成在阻挡层上的栅极介电层，形成在栅极介质上的栅极 邻近量子阱层和阻挡层形成的第一金属侧壁衬垫，邻近量子阱层和阻挡层形成的第二金属侧壁衬垫，与第一金属侧壁衬垫相邻的金属源极区域， 以及与第二金属侧壁衬垫相邻的金属漏极区域。<​​/ p>

公开(公告)号：WO2008076527A3

公开(公告)日：2008-06-26

申请号：PCT/US2007/082913

申请日：2007-10-29

申请人： INTEL CORPORATION ,  DATTA, Suman ,  KAVALIEROS, Jack ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert

发明人： DATTA, Suman ,  KAVALIEROS, Jack ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert

IPC分类号： H01L29/812 ,  H01L29/778

摘要： A group III-V material device may have a capping layer on a barrier region, which may provide a high quality interface for a high-k gate dielectric. This may improve the performance of the device by reducing gate leakage and preserve the high-mobility properties of the quantum well channel region of the device.

公开(公告)号：WO2008076527A2

公开(公告)日：2008-06-26

申请号：PCT/US2007082913

申请日：2007-10-29

申请人： INTEL CORP ,  DATTA SUMAN ,  KAVALIEROS JACK ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT

发明人： DATTA SUMAN ,  KAVALIEROS JACK ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT

CPC分类号： H01L29/7783 ,  H01L29/517

摘要： A group III-V material device may have a capping layer on a barrier region, which may provide a high quality interface for a high-k gate dielectric. This may improve the performance of the device by reducing gate leakage and preserve the high-mobility properties of the quantum well channel region of the device.

摘要翻译： III-V族材料器件可以在阻挡区域上具有覆盖层，这可为高k栅极电介质提供高质量的界面。 这可以通过减少栅极泄漏并且保持器件的量子阱沟道区域的高迁移率特性来改善器件的性能。

公开(公告)号：WO2006050283A2

公开(公告)日：2006-05-11

申请号：PCT/US2005/039310

申请日：2005-10-28

申请人： INTEL CORPORATION ,  DOYLE, Brian ,  BRASK, Justin ,  DATTA, Suman ,  KAVALIEROS, Jack ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert ,  MAJUMDAR, Amlan

发明人： DATTA, Suman ,  KAVALIEROS, Jack ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert ,  MAJUMDAR, Amlan

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/76 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

摘要： An embodiment of the present invention is a technique to fabricate a semiconductor device having low off state leakage current. A gate structure of a first device is formed on a substrate layer having a hardmask. A channel is formed underneath the gate structure having a width to support the gate structure. An oxide or a dielectric layer is deposited on the substrate layer. A doped polysilicon layer is deposited on the oxide layer. A recessed junction area is formed on the doped polysilicon layer between the first device and an adjacent device.

摘要翻译： 本发明的一个实施例是制造具有低关断状态的漏电流的半导体器件的技术。 第一器件的栅极结构形成在具有硬掩模的衬底层上。 沟道形成在具有支撑栅极结构的宽度的栅极结构下方。 氧化物或电介质层沉积在衬底层上。 掺杂的多晶硅层沉积在氧化物层上。 在第一器件和相邻器件之间的掺杂多晶硅层上形成凹入的接合区域。

公开(公告)号：WO2018125203A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069470

申请日：2016-12-30

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  FISCHER, Paul B.

发明人： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  FISCHER, Paul B.

IPC分类号： H01L21/768 ,  H01L21/3215

摘要： A guard ring structure includes a ring of semiconductor material disposed on a substrate. A conductive ring is disposed on the ring of semiconductor material. The conductive ring is interconnected by intervening vias. The guard ring structure may include a plurality of individual rings of the semiconductor material formed concentrically and in close proximity to one another on the substrate. A Guard ring structure is generally disposed around a periphery of a die containing integrated circuits that include transistors RF amplifiers and memory devices to reduce the impact of stresses arising from die sawing to separate individual die in a wafer.

公开(公告)号：WO2013101004A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067667

申请日：2011-12-28

申请人： Intel Corporation ,  PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  RACHMADY, Willy ,  LE, Van H. ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko

发明人： PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  RACHMADY, Willy ,  LE, Van H. ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

摘要： Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

摘要翻译： 本公开的实施例提供了用于减小纳米线晶体管中的寄生电阻的接触技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的隔离层，包括在隔离层上形成的纳米线材料以提供晶体管沟道的沟道层，以及与沟道层耦合的接触点 被配置为在至少一个平面尺寸中围绕所述沟道层的纳米线材料并且为所述晶体管提供源极端子或漏极端子。

公开(公告)号：WO2013101001A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067661

申请日：2011-12-28

申请人： INTEL CORPORATION ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  POWERS, James M. ,  LE, Van H. ,  CHU-KING, Benjamin ,  LEMAY, Mark R. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  CHOW, Loren ,  TOLCHINSKY, Peter G. ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

发明人： MUKHERJEE, Niloy ,  METZ, Matthew V. ,  POWERS, James M. ,  LE, Van H. ,  CHU-KING, Benjamin ,  LEMAY, Mark R. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  CHOW, Loren ,  TOLCHINSKY, Peter G. ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

IPC分类号： H01L21/20 ,  H01L29/778

CPC分类号： H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

摘要翻译： 描述了在非天然表面上形成具有降低的表面粗糙度和体缺陷密度的异质层以及由此形成的器件的方法。 在一个实施例中，该方法包括提供具有晶格常数的顶表面并在衬底的顶表面上沉积第一层的衬底。 第一层具有不同于衬底顶表面的第一晶格常数的晶格常数的顶表面。 第一层被退火和抛光以形成抛光表面。 然后在抛光表面上方沉积第二层。

公开(公告)号：WO2012092038A2

公开(公告)日：2012-07-05

申请号：PCT/US2011/066271

申请日：2011-12-20

申请人： INTEL CORPORATION ,  MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert S. ,  METZ, Matthew V.

发明人： MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert S. ,  METZ, Matthew V.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28575 ,  H01L29/66446

摘要： A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

摘要翻译： 一般介绍通过在源极和漏极中使用III-V半导体中间层来减少n沟道晶体管的接触电阻的方法。 就此而言，引入包括具有源极区和漏极区的n型晶体管的器件，邻近晶体管的第一层间电介质层，穿过第一层间电介质层到源极区的沟槽以及位于源极区和源极区之间的导电源触点 沟槽，源极触点通过III-V半导体中间层与源极区域分开。 其他实施例也被公开和要求保护。

公开(公告)号：WO2011087610A3

公开(公告)日：2011-10-20

申请号：PCT/US2010058784

申请日：2010-12-02

申请人： INTEL CORP ,  KAVALIEROS JACK T ,  RACHMADY WILLY ,  MUKHERJEE NILOY ,  RADOSAVLJEVIC MARKO ,  GOE NITI ,  LEE YONG JU ,  MAJHI PRASHANT ,  TSAI WILMAN ,  DEWEY GILBERT

发明人： KAVALIEROS JACK T ,  RACHMADY WILLY ,  MUKHERJEE NILOY ,  RADOSAVLJEVIC MARKO ,  GOE NITI ,  LEE YONG JU ,  MAJHI PRASHANT ,  TSAI WILMAN ,  DEWEY GILBERT

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

摘要翻译： 描述了III-V半导体器件的导电性改进。 第一种改进包括与沟道层不共面的平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源极/漏极。 第三种改进包括在III-V沟道层上形成IV族和/或VI族元素层，并退火以III-V族沟道层掺杂IV族和/或VI族物质。 第四种改进包括形成在III-V器件的接入区域上方的钝化层和/或偶极子层。