公开(公告)号：WO2006076087A3

公开(公告)日：2006-07-20

申请号：PCT/US2005/043555

申请日：2005-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CALLEGARI, Alessandro C. ,  FRANK, Martin M. ,  JAMMY, Rajarao ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  ZAFAR, Sufi

Inventor： CALLEGARI, Alessandro C. ,  FRANK, Martin M. ,  JAMMY, Rajarao ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  ZAFAR, Sufi

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/336

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：WO2006076087A2

公开(公告)日：2006-07-20

申请号：PCT/US2005043555

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L29/94

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

Abstract translation: 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）的高温下退火HfSiN /高k电介质/界面层之后，界面层的减少，因此栅叠层产生非常小的等效氧化物厚度 （12经典），使用TaSiN无法实现。

公开(公告)号：WO2006055226A3

公开(公告)日：2007-08-23

申请号：PCT/US2005039288

申请日：2005-11-01

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract translation: 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：WO2007050312A2

公开(公告)日：2007-05-03

申请号：PCT/US2006039940

申请日：2006-10-12

Applicant: IBM ,  CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO 2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

Abstract translation: 一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电常数的介电材料和至少一种用于 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：WO2005122286A2

公开(公告)日：2005-12-22

申请号：PCT/US2005/010825

申请日：2005-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BOJARCZUK, Nestor A., Jr. ,  CABRAL, Cyril, Jr. ,  CARTIER, Eduard A. ,  COPEL, Matthew W. ,  FRANK, Martin M. ,  GOUSEV, Evgeni P. ,  GUHA, Supratik ,  JAMMY, Rajarao ,  NARAYANAN, Vijay ,  PARUCHURI, Vamsi K.

Inventor： BOJARCZUK, Nestor A., Jr. ,  CABRAL, Cyril, Jr. ,  CARTIER, Eduard A. ,  COPEL, Matthew W. ,  FRANK, Martin M. ,  GOUSEV, Evgeni P. ,  GUHA, Supratik ,  JAMMY, Rajarao ,  NARAYANAN, Vijay ,  PARUCHURI, Vamsi K.

IPC: H01L31/113

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxN Y . The high k dielectric can be HfO 2 , hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H 2 O 2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2012121852A1

公开(公告)日：2012-09-13

申请号：PCT/US2012/025411

申请日：2012-02-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  BROWN, Stephen L. ,  BRULEY, John ,  CABRAL JR., Cyril ,  CALLEGARI, Sandro ,  FRANK, Martin M. ,  GUILLORN, Michael A. ,  HOPSTAKEN, Marinus ,  NARAYANAN, Vijay ,  KWONG HON WONG, Keith

Inventor： BROWN, Stephen L. ,  BRULEY, John ,  CABRAL JR., Cyril ,  CALLEGARI, Sandro ,  FRANK, Martin M. ,  GUILLORN, Michael A. ,  HOPSTAKEN, Marinus ,  NARAYANAN, Vijay ,  KWONG HON WONG, Keith

IPC: H01L21/70 ,  C23C14/06 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L23/53266 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.

Abstract translation: 层状结构和半导体器件以及用于制造层状结构和半导体器件的方法。 层状结构包括：包含含有氮化钛，氮化钽或其组合的材料的基底层; 包括含有氮化铝钽，氮化铝钛，氮化硅，氮化钛，氮化钽，氮化钛，氮化铪，碳化铪，碳化钽，氮化钒，氮化铌或其组合的材料的导电层 物; 和钨层。 半导体器件包括：半导体衬底; 基层; 导电层; 和钨层。

公开(公告)号：WO2011123238A1

公开(公告)日：2011-10-06

申请号：PCT/US2011/028422

申请日：2011-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  DUBOURDIEU, Catherine A. ,  FRANK, Martin M.

Inventor： DUBOURDIEU, Catherine A. ,  FRANK, Martin M.

IPC: H01L21/00

CPC classification number: H01L21/28291 ,  H01L28/55 ,  H01L29/66636 ,  H01L29/6684 ,  H01L29/7804 ,  H01L29/78391 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

Abstract translation: 控制集成电路器件部件的铁电特性的方法包括在衬底上形成铁电可控的电介质层; 以及在所述铁电可控电介质层附近形成应力施加结构，使得通过所述应力施加结构在所述铁电可控电介质层中诱发基本上单轴应变; 其中所述铁电可控介电层包括以下中的一种或多种：在没有施加应力的情况下不表现出铁电性能的铁电氧化物层和正常非铁电材料层。

公开(公告)号：WO2007050312A3

公开(公告)日：2007-05-03

申请号：PCT/US2006/039940

申请日：2006-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CARTER, Eduard, A. ,  COPEL, Matthew, W. ,  FRANK, Martin, M. ,  GOUSEV, Evgeni, P. ,  JAMISON, Paul, C. ,  JAMMY, Rajarao ,  LINDER, Barry, P. ,  NARAYANAN, Vijay

Inventor： CARTER, Eduard, A. ,  COPEL, Matthew, W. ,  FRANK, Martin, M. ,  GOUSEV, Evgeni, P. ,  JAMISON, Paul, C. ,  JAMMY, Rajarao ,  LINDER, Barry, P. ,  NARAYANAN, Vijay

IPC: H01L29/76

Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO 2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

公开(公告)号：WO2006055226A2

公开(公告)日：2006-05-26

申请号：PCT/US2005/039288

申请日：2005-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BOJARCZUK, Nestor A., Jr. ,  CABRAL, Cyril, Jr. ,  CARTIER, Eduard A. ,  FRANK, Martin M. ,  GOUSEV, Evgeni P. ,  GUHA, Supratik ,  JAMISON, Paul C. ,  JAMMY, Rajarao ,  NARAYANAN, Vijay ,  PARUCHURI, Vamsi K.

Inventor： BOJARCZUK, Nestor A., Jr. ,  CABRAL, Cyril, Jr. ,  CARTIER, Eduard A. ,  FRANK, Martin M. ,  GOUSEV, Evgeni P. ,  GUHA, Supratik ,  JAMISON, Paul C. ,  JAMMY, Rajarao ,  NARAYANAN, Vijay ,  PARUCHURI, Vamsi K.

IPC: H01L29/94

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract translation: 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：WO2012078456A1

公开(公告)日：2012-06-14

申请号：PCT/US2011/062970

申请日：2011-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DUBOURDIEU, Catherine A. ,  FRANK, Martin M. ,  RAJENDRAN, Bipin ,  SCHROTT, Alejandro G.

Inventor： DUBOURDIEU, Catherine A. ,  FRANK, Martin M. ,  RAJENDRAN, Bipin ,  SCHROTT, Alejandro G.

IPC: G11C11/00

CPC classification number: H01L45/1608 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0095 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.

Abstract translation: 所公开的示例实施例是相变存储单元。 存储单元包括相变材料和位于相变材料附近的换能器。 相变材料可在至少非晶状态和结晶状态之间切换。 换能器被配置为当相变材料从非晶状态转变为结晶态时激活。 在特定实施例中，换能器是铁电材料。