公开(公告)号：WO2005045892A9

公开(公告)日：2006-06-22

申请号：PCT/US2004035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

Inventor： MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer.

Abstract translation: 半导体制造工艺包括形成覆盖衬底的硅片。 形成在鳍片的主面上的栅极电介质。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶并蚀刻通过覆盖层。

公开(公告)号：WO2007050317A2

公开(公告)日：2007-05-03

申请号：PCT/US2006040019

申请日：2006-10-11

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R

Inventor： MATHEW LEO ,  MORA RODE R

IPC: H01L21/338

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for creating an inverse T field effect transistor (10) is provided. The method includes creating a horizontal active region (14) and a vertical active region (16) on a substrate (12). The method further comprises forming a sidewall spacer (22) on a first side of the vertical active region and a second side of the vertical active region (16). The method further includes removing a portion of the horizontal active region (14), which is not covered by the sidewall spacer (22). The method further includes removing the sidewall spacer (22). The method further includes forming a gate dielectric (26) over at least a first part of the horizontal active region (14) and at least a first part of the vertical active region (16). The method further includes forming a gate electrode (28) over the gate dielectric (26). The method further includes forming a source region (30) and a drain region (32) over at least a second part of the horizontal active region and at least a second part of the vertical active region (16).

Abstract translation: 提供了一种用于创建逆T型场效应晶体管（10）的方法。 该方法包括在衬底（12）上创建水平有源区域（14）和垂直有源区域（16）。 该方法进一步包括在垂直有源区的第一侧和垂直有源区（16）的第二侧上形成侧壁间隔物（22）。 该方法还包括去除没有被侧壁间隔物（22）覆盖的水平有源区（14）的一部分。 该方法还包括去除侧壁间隔件（22）。 该方法还包括在水平有源区（14）的至少第一部分和垂直有源区（16）的至少第一部分上形成栅极电介质（26）。 该方法还包括在栅极电介质（26）上形成栅电极（28）。 该方法还包括在水平有源区的至少第二部分和垂直有源区（16）的至少第二部分之上形成源极区（30）和漏极区（32）。

公开(公告)号：WO2005045892A2

公开(公告)日：2005-05-19

申请号：PCT/US2004035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

Inventor： MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

Abstract translation: 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

公开(公告)号：WO2006104562A3

公开(公告)日：2008-01-10

申请号：PCT/US2006003528

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  KOLAGUNTA VENKAT R ,  SING DAVID C

Inventor： MATHEW LEO ,  KOLAGUNTA VENKAT R ,  SING DAVID C

IPC: H01L21/425 ,  H01L23/58

CPC classification number: H01L29/7835 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/785 ,  H01L29/78624 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

Abstract: A method for forming a semiconductor device (10) including forming a semiconductor substrate (12); forming a gate electrode (16) over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area (42) under the gate electrode and adjacent the first side of the gate electrode, a second area (44) under the gate electrode and adjacent the second side of the gate electrode, and a third area (14) under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

Abstract translation: 一种形成半导体器件（10）的方法，包括形成半导体衬底（12）; 在所述半导体衬底上形成具有第一侧和第二侧的栅电极，以及在所述栅电极下形成栅电介质。 所述栅极电介质具有位于所述栅电极下方且与所述栅电极的第一侧相邻的第一区域（42），所述栅电极下方的第二区域（44）和所述栅电极的第二侧相邻，以及第三区域 ）在所述第一区域和所述第二区域之间的所述栅极电极下方，其中所述第一区域比所述第二区域薄，并且所述第三区域比所述第一区域薄，并且比所述第二区域薄。

公开(公告)号：WO2007117774A2

公开(公告)日：2007-10-18

申请号：PCT/US2007062557

申请日：2007-02-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MURALIDHAR RAMACHANDRAN ,  DHANDAPANI VEERARAGHAVAN

Inventor： MATHEW LEO ,  MURALIDHAR RAMACHANDRAN ,  DHANDAPANI VEERARAGHAVAN

IPC: H01L21/3205

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833

Abstract: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions (109, 107) of different heights. In one example, the structure is removed by forming a spacer (203) over the lower portion adjacent to the sidewall of the higher portion. A second material (303) is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.

Abstract translation: 去除半导体器件中的一部分结构以分离结构。 该结构具有不同高度的两个部分（109,107）。 在一个示例中，通过在与较高部分的侧壁相邻的下部分上形成间隔物（203）来移除结构。 然后在间隔件外部的结构上形成第二材料（303）。 移除间隔物，然后移除间隔物下面的部分以在该位置分离结构。 在一个实施例中，在分离的结构中实现单独的通道区域。 在其他实施例中，在分离的结构中实现单独的门结构。

公开(公告)号：WO2007044190A2

公开(公告)日：2007-04-19

申请号：PCT/US2006036703

申请日：2006-09-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  RAO RAJESH A ,  MURALIDHAR RAMACHANDRAN

Inventor： MATHEW LEO ,  RAO RAJESH A ,  MURALIDHAR RAMACHANDRAN

IPC: H01L29/76 ,  H01L21/302 ,  H01L21/461 ,  H01L29/745

CPC classification number: H01L29/42368 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/32139 ,  H01L28/91 ,  H01L29/512 ,  H01L29/513

Abstract: A semiconductor device (10) includes a plurality of pillars (22) formed from a conductive material (16). The pillars are formed by using a plurality of nanocrystals (20) as a hardmask for patterning the conductive material (16). A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal (20). In one embodiment, the pillars (22) are formed from polysilicon and function as the charge storage region of a non-volatile memory cell (25) having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor (50) having an increased capacitance without increasing the surface area of an integrated circuit.

Abstract translation: 半导体器件（10）包括由导电材料（16）形成的多个支柱（22）。 柱通过使用多个纳米晶体（20）作为用于图案化导电材料（16）的硬掩模形成。 导电材料的厚度决定了支柱的高度。 同样地，柱的宽度由纳米晶体（20）的直径确定。 在一个实施例中，柱（22）由多晶硅形成并用作具有良好电荷保持和低电压操作的非易失性存储单元（25）的电荷存储区域。 在另一个实施例中，支柱由金属形成，并且作为具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器（50）的平板电极而起作用，而不增加集成电路的表面积。

公开(公告)号：WO2007120293A3

公开(公告)日：2008-11-06

申请号：PCT/US2006061283

申请日：2006-11-28

Applicant: FREESCALE SEMICONDUCTOR INC ,  BURNETT JAMES D ,  MATHEW LEO ,  MIN BYOUNG W

Inventor： BURNETT JAMES D ,  MATHEW LEO ,  MIN BYOUNG W

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A process for forming an electronic device can include forming a semiconductor fin (18) of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin (934) is shortened to a second height. In accordance with specific embodiment a second semiconductor fin (932) can be formed, each of the first (934) and the second (932) semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second (932) and a third semiconductor fin (938) can be formed, each of the first (934), the second (932) and the third semiconductor fins (938) having a different height representing a channel width.

Abstract translation: 一种用于形成电子器件的方法可以包括形成用于鳍型结构的第一高度的半导体鳍片（18），并且去除半导体鳍片的一部分，使得半导体鳍片（934）被缩短到第二高度。 根据具体实施例，可以形成第二半导体翅片（932），第一（934）和第二（932）半导体鳍片中的每一个具有表示通道宽度的不同高度。 根据另一个具体实施例，可以形成第二（932）和第三半导体翅片（938），第一（934），第二（932）和第三半导体翅片（938）中的每一个具有不同的高度， 信道宽度。

公开(公告)号：WO2007050288A3

公开(公告)日：2008-01-03

申请号：PCT/US2006039651

申请日：2006-10-10

Applicant: FREESCALE SEMICONDUCTOR INC ,  MIN BYOUNG W ,  BURNETT JAMES D ,  MATHEW LEO

Inventor： MIN BYOUNG W ,  BURNETT JAMES D ,  MATHEW LEO

IPC: H01L21/4763 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for making a semiconductor device (10) is provided. The method includes forming a first transistor (94) with a vertical active region (56) and a horizontal active region (54) extending on both sides of the vertical active region (56). The method further includes forming a second transistor (96) with a vertical active region (58). The method further includes forming a third transistor (98) with a vertical active region (60) and a horizontal active region (54) extending on only one side of the vertical active region (60).

Abstract translation: 提供一种制造半导体器件（10）的方法。 该方法包括形成具有在垂直有源区（56）的两侧延伸的垂直有源区（56）和水平有源区（54）的第一晶体管（94）。 该方法还包括形成具有垂直有源区（58）的第二晶体管（96）。 该方法还包括形成具有仅在垂直有源区域（60）的一侧上延伸的垂直有源区域（60）和水平有源区域（54）的第三晶体管（98）。

公开(公告)号：WO2007047164A3

公开(公告)日：2007-09-27

申请号：PCT/US2006039177

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC ,  KALPAT SRIRAM S ,  MATHEW LEO ,  MOOSA MOHAMED S ,  SADD MICHAEL A ,  SANCHEZ HECTOR

Inventor： KALPAT SRIRAM S ,  MATHEW LEO ,  MOOSA MOHAMED S ,  SADD MICHAEL A ,  SANCHEZ HECTOR

IPC: H03B1/00

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

Abstract: A voltage controlled oscillator (VCO) (40) has a plurality (42, 44, 46) of series-connected inverters. Within each inverter a first transistor (48) has a first current electrode coupled to a first power supply voltage terminal (VDD), a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series connected inverters, and a second control electrode for receiving a first bias signal. A second transistor (50) has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal (Vss), and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal (VGp, VPP OR DNP) to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract translation: 压控振荡器（VCO）（40）具有多个（42,44,46）串联逆变器。 在每个逆变器内，第一晶体管（48）具有耦合到第一电源电压端子（VDD）的第一电流电极，第二电流电极，耦合到多个串联连接的逆变器中的另一个反相器的输出端子的第一控制电极 以及用于接收第一偏置信号的第二控制电极。 第二晶体管（50）具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电源电压端子（Vss）的第二电流电极，以及耦合到第一控制电极的第一控制电极的第一控制电极 第一个晶体管。 每个逆变器的第一晶体管的第二控制电极接收相同或分开的模拟控制信号（VGp，VPP或DNP），以调整其第一晶体管的阈值电压以影响VCO信号的频率和相位。

公开(公告)号：WO2005048299A3

公开(公告)日：2005-11-17

申请号：PCT/US2004034810

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MURALIDHAR RAMACHANDRAN

Inventor： MATHEW LEO ,  MURALIDHAR RAMACHANDRAN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76

CPC classification number: H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters (143, 144), adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Abstract translation: 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层（例如纳米簇（143,144）），并通过三个栅极区域控制电荷存储层，使用相同的工艺来实现易失性和非易失性存储单元，以创建通用存储器 处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。