公开(公告)号：WO2007143289A1

公开(公告)日：2007-12-13

申请号：PCT/US2007/067285

申请日：2007-04-24

Applicant: FREESCALE SEMICONDUCTOR INC. ,  THEAN, Voon-yew ,  VARTANIAN, Victor H. ,  WINSTEAD, Brian A.

Inventor： THEAN, Voon-yew ,  VARTANIAN, Victor H. ,  WINSTEAD, Brian A.

IPC: H01L21/84

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/84

Abstract: A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer (101). The wafer's active layer (106) is biaxially strained and has first (110-1) and second regions (110-2). The second region (110-2) is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of transistors (150-1, 150-2) are fabricated in the first region and the second region respectively. Third (110-3) and possibly fourth regions (110-4) of the active layer may be processed to alter their strain characteristics. A sacrificial strain structure (130) may be formed overlying the third region. The strain structure may be a compressive. When annealing the wafer with the strain structure in place, its strain characteristics may be mirrored in the third active layer region (110-3). The fourth active layer region (110-4) may be amorphized in stripes that run parallel to a width direction of the transistor strain to produce uniaxial stress in the width direction.

Abstract translation: 半导体制造工艺优选与半导体绝缘体（SOI）晶片（101）一起使用。 晶片的有源层（106）是双轴应变的，并具有第一（110-1）和第二区（110-2）。 第二区域（110-2）非晶化以改变其应变分量。 将晶片退火以使非晶半导体再结晶。 分别在第一区域和第二区域中制造第一和第二类型的晶体管（150-1,150-2）。 可以处理活性层的第三（110-3）和可能的第四区（110-4）以改变它们的应变特性。 可以在第三区域上形成牺牲应变结构（130）。 应变结构可以是压缩的。 当将具有应变结构的晶片退火就位时，其应变特性可以反映在第三有源层区域（110-3）中。 第四有源层区域（110-4）可以以与晶体管应变的宽度方向平行的条状非晶化，以在宽度方向上产生单轴应力。

公开(公告)号：WO2006039038A2

公开(公告)日：2006-04-13

申请号：PCT/US2005/031001

申请日：2005-08-31

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  THEAN, Voon-Yew ,  SADAKA, Mariam G. ,  WHITE, Ted R. ,  BARR, Alexander L. ,  KOLAGUNTA, Venkat R. ,  NGUYEN, Bich-Yen ,  VARTANIAN, Victor H. ,  ZHANG, Da

Inventor： THEAN, Voon-Yew ,  SADAKA, Mariam G. ,  WHITE, Ted R. ,  BARR, Alexander L. ,  KOLAGUNTA, Venkat R. ,  NGUYEN, Bich-Yen ,  VARTANIAN, Victor H. ,  ZHANG, Da

IPC: H01L21/336

CPC classification number: H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Abstract translation: 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：WO2006020282A1

公开(公告)日：2006-02-23

申请号：PCT/US2005/025536

申请日：2005-07-15

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ZHANG, Da ,  GOOLSBY, Brian, J. ,  LUCKOWSKI, Eric,D. ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam, G. ,  THEAN, Voon-Yew ,  WHITE, Ted, R.

Inventor： ZHANG, Da ,  GOOLSBY, Brian, J. ,  LUCKOWSKI, Eric,D. ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam, G. ,  THEAN, Voon-Yew ,  WHITE, Ted, R.

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/78687

Abstract: A method for forming at least a portion of a semiconductor device (10, 50) includes providing a substrate (12) and epitaxially forming an etch stop layer (14) over the substrate. A first layer (16) is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure (20) is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion (28, 52) of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer (36, 54) is epitaxially grown in the etch-recessed region.

Abstract translation: 用于形成半导体器件（10,50）的至少一部分的方法包括提供衬底（12）并在衬底上外延形成蚀刻停止层（14）。 第一层（16）设置在蚀刻停止层上方，其中第一层相对于蚀刻停止层可选择性地蚀刻。 在第一层的区域上提供结构（20），其中该区域不是全部第一层。 此外，该方法包括蚀刻在区域外部的第一层的至少一部分（28,52），其中蚀刻停止层用作蚀刻停止。 在蚀刻凹陷区域中外延生长应变层（36,54）。

公开(公告)号：WO2005081748A2

公开(公告)日：2005-09-09

申请号：PCT/US2005/001532

申请日：2005-01-12

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BARR, Alexander, L. ,  JOVANOVIC, Dejan ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam, G. ,  THEAN, Voon-Yew ,  WHITE, Ted, R.

Inventor： BARR, Alexander, L. ,  JOVANOVIC, Dejan ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam, G. ,  THEAN, Voon-Yew ,  WHITE, Ted, R.

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84

Abstract: A first semiconductor structure (10) has a silicon substrate (12), a first silicon germanium layer (14) grown on the silicon, a second silicon germanium layer (16) on the first silicon germanium layer (14), and a strained silicon layer (18) on the second silicon germanium layer (16). A second semiconductor structure (22) has a silicon substrate (24) and an insulating top layer (26). The silicon layer (18) of the first semiconductor structure (10) is bonded to the insulator layer (26) to form a third semiconductor structure (30). The second silicon germanium layer (16) is cut to separate most of the first semiconductor structure (10) from the third semiconductor structure (30). The silicon germanium layer (16) is removed to expose the strained silicon layer (18) where transistors (32 & 34) are subsequently formed, which is then the only layer remaining from the first semiconductor structure (10). The transistors (32 & 34) are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer (24) of the second semiconductor structure.

Abstract translation: 第一半导体结构（10）具有硅衬底（12），在硅上生长的第一硅锗层（14），第一硅锗层（14）上的第二硅锗层（16）和应变硅 层（18）在第二硅锗层（16）上。 第二半导体结构（22）具有硅衬底（24）和绝缘顶层（26）。 第一半导体结构（10）的硅层（18）与绝缘体层（26）接合形成第三半导体结构（30）。 切割第二硅锗层（16）以将大部分第一半导体结构（10）与第三半导体结构（30）分离。 硅锗层（16）被去除以暴露其后形成晶体管（32和34）的应变硅层（18），然后是从第一半导体结构（10）剩余的唯一层。 晶体管（32和34）沿第一半导体结构的基极硅层（24）的<100>方向和<100>方向成45度角定向。

公开(公告)号：WO2007130728A3

公开(公告)日：2008-11-06

申请号：PCT/US2007062534

申请日：2007-02-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  SADAKA MARIAM G ,  NGUYEN BICH-YEN ,  THEAN VOON-YEW

Inventor： SADAKA MARIAM G ,  NGUYEN BICH-YEN ,  THEAN VOON-YEW

IPC: H01L21/8238

CPC classification number: H01L21/32 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/84

Abstract: A process of forming an electronic device can include forming a patterned oxidation-resistant layer (124) over a semiconductor layer (106) that overlies a substrate (100), and patterning the semiconductor layer to form a semiconductor island (202, 204, 206, 208). The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material (424) along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.

Abstract translation: 形成电子器件的工艺可以包括在覆盖在衬底（100）上的半导体层（106）上形成图案化的抗氧化层（124），并且图案化半导体层以形成半导体岛（202,204,206 ，208）。 半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。 该方法还可以包括沿着半导体岛的一侧形成抗氧化材料（424）或沿着半导体岛的一侧选择性地沉积半导体材料。 该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛， 并将抗氧化材料转化为含氧环境。

公开(公告)号：WO2007053339A3

公开(公告)日：2007-05-10

申请号：PCT/US2006/041146

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC. ,  THEAN, Voon-Yew ,  CHEN, Jian ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam G. ,  ZHANG, Da

Inventor： THEAN, Voon-Yew ,  CHEN, Jian ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam G. ,  ZHANG, Da

IPC: H01L31/00

Abstract: Forming a semiconductor structure includes providing a substrate (10) having a strained semiconductor layer (14) overlying an insulating layer (12), providing a first device region (18) for forming a first plurality of devices having a first conductivity type, providing a second device region (20) for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region (18) having a first conductivity type, forming an insulating layer (34) overlying at least an active area (32) of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material (46) overlying at least a portion of the insulating layer.

公开(公告)号：WO2007053339A2

公开(公告)日：2007-05-10

申请号：PCT/US2006041146

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  THEAN VOON-YEW ,  CHEN JIAN ,  NGUYEN BICH-YEN ,  SADAKA MARIAM G ,  ZHANG DA

Inventor： THEAN VOON-YEW ,  CHEN JIAN ,  NGUYEN BICH-YEN ,  SADAKA MARIAM G ,  ZHANG DA

IPC: H01L21/84

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7842 ,  H01L29/785 ,  Y10S438/938

Abstract: Forming a semiconductor structure includes providing a substrate (10) having a strained semiconductor layer (14) overlying an insulating layer (12), providing a first device region (18) for forming a first plurality of devices having a first conductivity type, providing a second device region (20) for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region (18) having a first conductivity type, forming an insulating layer (34) overlying at least an active area (32) of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material (46) overlying at least a portion of the insulating layer.

Abstract translation: 形成半导体结构包括提供具有覆盖在绝缘层（12）上的应变半导体层（14）的衬底（10），提供用于形成具有第一导电类型的第一多个器件的第一器件区域（18） 用于形成具有第二导电类型的第二多个器件的第二器件区域（20），并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的应变半导体层的应变 第一个设备区域。 或者，形成半导体结构包括提供具有第一导电类型的第一区域（18），形成覆盖第一区域的至少有源区域（32）的绝缘层（34），各向异性地蚀刻绝缘层，以及各向异性 蚀刻绝缘层，去除覆盖绝缘层的至少一部分的栅电极材料（46）。

公开(公告)号：WO2006103066A1

公开(公告)日：2006-10-05

申请号：PCT/EP2006/002893

申请日：2006-03-30

Applicant: PAUL SCHERRER INSTITUT ,  GARCHING INNOVATIONS GMBH ,  NGUYEN, Bich-Yen ,  THOMAS, Shawn, G. ,  CERGEL, Lubomir ,  SADAKA, Mariam, G. ,  THEAN, Voon-Yew ,  WENNEKERS, Peter ,  WHITE, Ted, R. ,  WILD, Andreas, A. ,  GRUETZMACHER, Detlev ,  SCHMIDT, Oliver, G.

Inventor： NGUYEN, Bich-Yen ,  THOMAS, Shawn, G. ,  CERGEL, Lubomir ,  SADAKA, Mariam, G. ,  THEAN, Voon-Yew ,  WENNEKERS, Peter ,  WHITE, Ted, R. ,  WILD, Andreas, A. ,  GRUETZMACHER, Detlev ,  SCHMIDT, Oliver, G.

CPC classification number: H01L29/78696 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687

Abstract: A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. Ih addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.

Abstract translation: 半导体器件包括机械应变通道，其中所述通道包括具有非线性几何形状的应变半导体层的单晶结构，所述非线性几何形状包括拱形形状的一部分。 所述半导体器件还包括介电层，其中所述沟道的第一部分设置在所述电介质层内的点位置上方，并且所述沟道的第二部分设置在所述电介质层的靠近所述点位置和外侧的部分上方 。 此外，栅极靠近通道设置，用于控制电流通过耦合到通道的第一和第二电流处理电极之间的通道。

公开(公告)号：WO2006023492A1

公开(公告)日：2006-03-02

申请号：PCT/US2005/029113

申请日：2005-08-08

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  SADAKA, Mariam G. ,  THOMAS, Shawn G. ,  WHITE, Ted R. ,  LIU, Chun-Li ,  BARR, Alexander L. ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew

Inventor： SADAKA, Mariam G. ,  THOMAS, Shawn G. ,  WHITE, Ted R. ,  LIU, Chun-Li ,  BARR, Alexander L. ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew

IPC: H01L21/84

CPC classification number: H01L29/78687 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66742

Abstract: A process for forming a semiconductor device. The process includes forming a template layer (207) for forming a layer (305) of strained silicon. In one example a layer (107) of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

Abstract translation: 一种形成半导体器件的方法。 该方法包括形成用于形成应变硅层（305）的模板层（207）。 在一个示例中，形成梯度硅锗的层（107），其中锗在下部具有较高的浓度，在顶部处的浓度较低。 当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。 由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

公开(公告)号：WO2009017907A3

公开(公告)日：2009-04-09

申请号：PCT/US2008068088

申请日：2008-06-25

Applicant: FREESCALE SEMICONDUCTOR INC ,  DAO THUY B ,  THEAN VOON-YEW ,  WHITE BRUCE E

Inventor： DAO THUY B ,  THEAN VOON-YEW ,  WHITE BRUCE E

IPC: H01L27/108

CPC classification number: H01L29/66833 ,  B82Y10/00 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device (300) suitable for use as a storage cell includes a semiconductor body (302) having a top surface and a bottom surface, a top gate dielectric (145) overlying the semiconductor body top surface (302), an electrically conductive top gate electrode (161) overlying the top gate dielectric (145), a bottom gate dielectric (106) underlying the semiconductor body (302) bottom surface, an electrically conductive bottom gate electrode (108) underlying the bottom gate dielectric (106), and a charge trapping layer (104). The charge trapping layer (104) includes a plurality of shallow charge traps (104), adjacent the top or bottom surface of the semiconductor body. The charge trapping layer (104) may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer (104) may located positioned between the bottom gate dielectric (106) and the bottom surface of the semiconductor body (302).

Abstract translation: 适合用作存储单元的半导体器件（300）包括具有顶表面和底表面的半导体主体（302），覆盖半导体主体顶表面（302）的顶部栅极电介质（145），导电顶部 覆盖顶部栅极电介质145的栅极电极161，位于半导体主体302底部表面下方的底部栅极电介质106，位于底部栅极电介质106下方的导电底部栅极电极108以及 电荷俘获层（104）。 电荷俘获层（104）包括邻近半导体主体的顶部或底部表面的多个浅电荷陷阱（104）。 电荷俘获层（104）可以是氧化铝，氮化硅或硅纳米团簇。 电荷俘获层（104）可位于底部栅极电介质（106）与半导体主体（302）的底部表面之间。