Abstract:
An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.
Abstract:
Embodiments of the present disclosure are directed towards magnetic shielded integrated circuit (IC) package assemblies and materials for shielding integrated circuits from external magnetic fields. In one embodiment, a package assembly includes a die coupled with a package substrate and a mold compound disposed on the die. The mold compound includes a matrix component and magnetic field absorbing particles. Other embodiments may be described and/or claimed.
Abstract:
Described is an apparatus 1T-1 Magnetic Tunnel Junction (MTJ) Spin Hall Magnetic Random Access Memory (MRAM) bit-cell and array, and method of forming such. The apparatus comprises: a select line; an interconnect with Spin Hall Effect (SHE) material, the interconnect coupled to a write bit line; a transistor coupled to the select line and the interconnect, the transistor controllable by a word line; and a MTJ device having a free magnetic layer coupled to the interconnect.
Abstract:
A device including at least two spintronic devices and a method of making the same. A magnetic connector extends between the two spintronic devices to conduct a magnetization between the two. The magnetic connector may further be disposed to conduct current to switch a magnetization of one of the two spintronic devices.
Abstract:
The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
Abstract:
Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.
Abstract:
Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.
Abstract:
An integrated structure includes front and rear facets (201, 203) optically- coupled by a waveguide (220) passing through the integrated structure. The integrated structure includes a gain section (202) and a reflector (208) optically coupled to the gain section by the waveguide, the reflector to emit an optical output. A modulator (214) is optically coupled to the reflector by the waveguide, the modulator to modulate the optical output. And a control section (216) disposed along the waveguide.
Abstract:
Embodiments are generally directed to enhanced materials processing for magneto-electric spin orbit (MESO) devices. An embodiment of an apparatus includes a first transistor and a second transistor, each transistor including a gate electrode, a first junction region, and a second junction region; a set of lines including alternating ferromagnetic material lines and non-magnetic metal interconnect lines fabricated in a wafer, the plurality of lines including metal interconnect lines to provide connections for the junction regions of the first and second transistors, including connections to provide power and control; and a MESO device including a first magnet and a second magnet, the set of lines including ferromagnetic material lines for fabrication of the MESO device magnets.
Abstract:
Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic demultiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.