公开(公告)号：WO2011159583A4

公开(公告)日：2012-08-02

申请号：PCT/US2011040105

申请日：2011-06-10

Applicant: SANDISK 3D LLC ,  KREUPL FRANZ ,  BANDYOPADHYAY ABHIJIT ,  CHEN YUNG-TIN ,  FU CHU-CHEN ,  JAYASEKARA WIPUL PEMSIRI ,  KAI JAMES ,  MAKALA RAGHUVEER S ,  RABKIN PETER ,  SAMACHISA GEORGE ,  ZHANG JINGYAN

Inventor： KREUPL FRANZ ,  BANDYOPADHYAY ABHIJIT ,  CHEN YUNG-TIN ,  FU CHU-CHEN ,  JAYASEKARA WIPUL PEMSIRI ,  KAI JAMES ,  MAKALA RAGHUVEER S ,  RABKIN PETER ,  SAMACHISA GEORGE ,  ZHANG JINGYAN

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Abstract translation: 三维读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧具有第一和第二电阻转换层，并且在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极性或单极性切换特性。 在存储器单元的置位或复位操作中，离子电流在电阻切换层中流动，从而有助于切换机制。 由于导电中间层的散射，对开关机构没有贡献的电子流被减少，以避免损坏导向元件。 提供了用于RSME的不同层的特定材料和材料的组合。

公开(公告)号：WO2012087820A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/065472

申请日：2011-12-16

Applicant: SANDISK TECHNOLOGIES INC. ,  ALSMEIER, Johann ,  PURAYATH, Vinod ,  KAI, James ,  MATAMIS, George

Inventor： ALSMEIER, Johann ,  PURAYATH, Vinod ,  KAI, James ,  MATAMIS, George

IPC: H01L21/28 ,  H01L21/8247 ,  H01L29/788 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

Abstract: A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.

Abstract translation: 一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极和多个导电鳍片。 多个导电翅片中的每一个位于多个浮动栅极之一上。 多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极。 多个控制栅极中的每一个位于与多个浮动栅极和多个导电散热片中的每一个相邻的位置。

公开(公告)号：WO2012003301A3

公开(公告)日：2012-04-19

申请号：PCT/US2011042566

申请日：2011-06-30

Applicant: SANDISK TECHNOLOGIES INC ,  ALSMEIER JOHANN ,  PURAYATH VINOD ,  CHIEN HENRY ,  MATAMIS GEORGE ,  LEE YAO-SHENG ,  KAI JAMES ,  ZHANG YUAN ,  SAMACHISA GEORGE

Inventor： ALSMEIER JOHANN ,  PURAYATH VINOD ,  CHIEN HENRY ,  MATAMIS GEORGE ,  LEE YAO-SHENG ,  KAI JAMES ,  ZHANG YUAN ,  SAMACHISA GEORGE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/78642 ,  H01L29/7889 ,  H01L29/7926

Abstract: Monolithic, three dimensional NAND strings and manufacturing methods are disclosed. The channel (1) of the strings can be vertical or V-shaped. The core the channel can be filled with an insulator. The control gates ( 3 ) are recessed with respect to intermediate dielectric layers. The charge storage regions ( 9 ) and the blocking dielectric (7) are formed in the recesses. Shielding wings (12) can be formed next to the control gates.

Abstract translation: 公开了单片三维NAND串和制造方法。 弦的通道（1）可以是垂直的或V形的。 通道的芯可以填充绝缘体。 控制栅极（3）相对于中间介电层凹陷。 电荷存储区（9）和阻挡电介质（7）形成在凹部中。 屏蔽翼（12）可以在控制门旁边形成。

公开(公告)号：WO2011159581A3

公开(公告)日：2012-04-19

申请号：PCT/US2011040103

申请日：2011-06-10

Applicant: SANDISK 3D LLC ,  KREUPL FRANZ ,  COSTA XIYING ,  KAI JAMES ,  MAKALA RAGHUVEER S

Inventor： KREUPL FRANZ ,  COSTA XIYING ,  KAI JAMES ,  MAKALA RAGHUVEER S

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Abstract translation: 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。 离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

公开(公告)号：WO2012003301A2

公开(公告)日：2012-01-05

申请号：PCT/US2011/042566

申请日：2011-06-30

Applicant: SANDISK TECHNOLOGIES INC. ,  ALSMEIER, Johann ,  PURAYATH, Vinod ,  CHIEN, Henry ,  MATAMIS, George ,  LEE, Yao-Sheng ,  KAI, James ,  ZHANG, Yuan ,  SAMACHISA, George

Inventor： ALSMEIER, Johann ,  PURAYATH, Vinod ,  CHIEN, Henry ,  MATAMIS, George ,  LEE, Yao-Sheng ,  KAI, James ,  ZHANG, Yuan ,  SAMACHISA, George

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/66833 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/78642 ,  H01L29/7889 ,  H01L29/7926

Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Abstract translation: 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：WO2011011525A1

公开(公告)日：2011-01-27

申请号：PCT/US2010/042766

申请日：2010-07-21

Applicant: SANDISK CORPORATION ,  PURAYATH, Vinod, Robert ,  KAI, James, K. ,  HIGASHITANI, Masaaki ,  ORIMOTO, Takashi ,  MATAMIS, George ,  CHIEN, Henry

Inventor： PURAYATH, Vinod, Robert ,  KAI, James, K. ,  HIGASHITANI, Masaaki ,  ORIMOTO, Takashi ,  MATAMIS, George ,  CHIEN, Henry

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76224 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/788 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/936

Abstract: Nanostructure-based charge storage regions (CSR1-CSR5) are included in non-volatile memory devices and integrated with the fabrication of select gates (SGl) and peripheral circuitry (PGl, PG2) One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

Abstract translation: 基于纳米结构的电荷存储区域（CSR1-CSR5）被包括在非易失性存储器件中，并与选择栅极（SG1）和外围电路（PG1，PG2）的制造集成在一个衬底上施加一个或多个纳米结构涂层 存储器阵列区域和外围电路区域。 提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。 在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层以在衬底的有源区上选择性地形成纳米结构。 自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

公开(公告)号：WO2010005878A1

公开(公告)日：2010-01-14

申请号：PCT/US2009/049620

申请日：2009-07-02

Applicant: SANDISK CORPORATION ,  LEE, Dana ,  CHIN, Henry ,  KAI, James ,  ORIMOTO, Takashi, Whitney ,  PURAYATH, Vinod, R. ,  MATAMIS, George

Inventor： LEE, Dana ,  CHIN, Henry ,  KAI, James ,  ORIMOTO, Takashi, Whitney ,  PURAYATH, Vinod, R. ,  MATAMIS, George

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324

Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

Abstract translation: 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

公开(公告)号：WO2008122012A2

公开(公告)日：2008-10-09

申请号：PCT/US2008/059035

申请日：2008-04-01

Applicant: SANDISK CORPORATION ,  KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

Inventor： KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

Abstract: Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

Abstract translation: 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

公开(公告)号：WO2013012682A3

公开(公告)日：2013-04-04

申请号：PCT/US2012046490

申请日：2012-07-12

Applicant: SANDISK TECHNOLOGIES INC ,  PURAYATH VINOD R ,  KAI JAMES K ,  PACHAMUTHU JAYAVEL ,  LIANG JARRETT JUN ,  MATAMIS GEORGE ,  HONMA RYOICHI

Inventor： PURAYATH VINOD R ,  KAI JAMES K ,  PACHAMUTHU JAYAVEL ,  LIANG JARRETT JUN ,  MATAMIS GEORGE ,  HONMA RYOICHI

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract translation: 包括多个铜互连的半导体器件。 多个铜互连的至少第一部分在顶面具有弯液面。 半导体器件还包括多个气隙，其中多个气隙中的每个气隙位于多个位线的至少第一部分的相邻对之间。

公开(公告)号：WO2011091416A1

公开(公告)日：2011-07-28

申请号：PCT/US2011/022400

申请日：2011-01-25

Applicant: SANDISK 3D LLC ,  PURAYATH, Vinod Robert ,  MATAMIS, George ,  KAI, James ,  ORIMOTO, Takashi

Inventor： PURAYATH, Vinod Robert ,  MATAMIS, George ,  KAI, James ,  ORIMOTO, Takashi

IPC: H01L27/10 ,  H01L27/102

CPC classification number: H01L27/101 ,  H01L27/1021

Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

Abstract translation: 一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个 的第二轨道沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开， 所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。 第一半导体轨道沿第一方向延伸。 第二半导体轨道沿与第一方向不同的第二方向延伸。