公开(公告)号：WO2012067738A1

公开(公告)日：2012-05-24

申请号：PCT/US2011/056130

申请日：2011-10-13

Applicant: SANDISK 3D LLC ,  RABKIN, Peter ,  SAMACHISA, George ,  SCHEUERLEIN, Roy, E.

Inventor： RABKIN, Peter ,  SAMACHISA, George ,  SCHEUERLEIN, Roy, E.

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092

Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

Abstract translation: 存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。 存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。 存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到 相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

公开(公告)号：WO2013155329A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/036213

申请日：2013-04-11

Applicant: SANDISK TECHNOLOGIES, INC. ,  RABKIN, Peter ,  HIGASHITANI, Masaaki

Inventor： RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/115 ,  H01L21/265 ,  G11C16/08

CPC classification number: H01L29/66757 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/04 ,  H01L21/26513 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1222 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates (229). The bodies (231) of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed of. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that are formed by etching holes in the layer in which word lines are formed. Gate electrodes (404) and gate dielectrics (402) may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes.

Abstract translation: 这里公开了用于制造具有字线（WL）选择门（229）的3D堆叠存储器件的技术。 WL选择栅极的主体（231）可以由字线形成的相同材料（例如，高掺杂多晶硅）形成。 可以通过各种技术（例如反掺杂）来实现在WL选择栅极的体内期望的掺杂分布。 WL选择栅极可以包括通过在其中形成字线的层中蚀刻孔而形成的TFT。 可以在孔中形成栅极（404）和栅极电介质（402）。 体可以形成在孔外的多晶硅中。

公开(公告)号：WO2013155325A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/036208

申请日：2013-04-11

Applicant: SANDISK TECHNOLOGIES, INC. ,  RABKIN, Peter ,  HIGASHITANI, Masaaki

Inventor： RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/115 ,  H01L21/265 ,  G11C16/08

CPC classification number: H01L29/66757 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/04 ,  H01L21/26513 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1222 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: Disclosed herein are 3D stacked memory devices having WL select gates (229). The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area (301) of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors (231, 402, 404). 3D decoding may be provided in a 3D stacked memory device using the WL select gates.

Abstract translation: 这里公开了具有WL选择门的3D堆叠存储器件（229）。 3D堆叠存储器件可以具有NAND串。 WL选择栅极可以位于与字线板的字线连接区域（301）相邻的位置。 字线板可以由字线驱动器驱动，并且可以具有许多字线。 WL选择门可以选择单个字线或字线组。 因此，可以选择整个块的较小单元。 这可能会降低电容负载。 WL选择栅极可以包括薄膜晶体管（231,402,404）。 可以使用WL选择门在3D堆叠存储器件中提供3D解码。

公开(公告)号：WO2011159583A4

公开(公告)日：2012-08-02

申请号：PCT/US2011040105

申请日：2011-06-10

Applicant: SANDISK 3D LLC ,  KREUPL FRANZ ,  BANDYOPADHYAY ABHIJIT ,  CHEN YUNG-TIN ,  FU CHU-CHEN ,  JAYASEKARA WIPUL PEMSIRI ,  KAI JAMES ,  MAKALA RAGHUVEER S ,  RABKIN PETER ,  SAMACHISA GEORGE ,  ZHANG JINGYAN

Inventor： KREUPL FRANZ ,  BANDYOPADHYAY ABHIJIT ,  CHEN YUNG-TIN ,  FU CHU-CHEN ,  JAYASEKARA WIPUL PEMSIRI ,  KAI JAMES ,  MAKALA RAGHUVEER S ,  RABKIN PETER ,  SAMACHISA GEORGE ,  ZHANG JINGYAN

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Abstract translation: 三维读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧具有第一和第二电阻转换层，并且在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极性或单极性切换特性。 在存储器单元的置位或复位操作中，离子电流在电阻切换层中流动，从而有助于切换机制。 由于导电中间层的散射，对开关机构没有贡献的电子流被减少，以避免损坏导向元件。 提供了用于RSME的不同层的特定材料和材料的组合。

公开(公告)号：WO2013155332A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/036217

申请日：2013-04-11

Applicant: SANDISK TECHNOLOGIES, INC. ,  RABKIN, Peter ,  HIGASHITANI, Masaaki

Inventor： RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66757 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/04 ,  H01L21/26513 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1222 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole.

Abstract translation: 本文公开了薄膜晶体管（TFT）和用于制造TFT的技术。 TFT的栅电极的主平面可以相对于TFT所在的水平多晶硅层垂直取向。 栅极电极和栅极电介质之间的界面可以相对于TFT所在的水平多晶硅层垂直取向。 TFT可以具有由多晶硅的水平层的厚度限定的沟道宽度。 TFT可以通过蚀刻多晶硅层中的孔而形成。 然后，可以通过在侧壁上沉积电介质和导体材料层而在孔中形成栅极电极和栅极电介质。 主体可以形成在孔外的多晶硅的水平层中。

公开(公告)号：WO2013078068A1

公开(公告)日：2013-05-30

申请号：PCT/US2012/065374

申请日：2012-11-15

Applicant: SANDISK TECHNOLOGIES, INC. ,  HIGASHITANI, Masaaki ,  RABKIN, Peter

Inventor： HIGASHITANI, Masaaki ,  RABKIN, Peter

IPC: H01L27/115 ,  H01L27/06 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L28/87

Abstract: Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric (L0, L2,...,L12) such as oxide and a conductive material (L1, L3,...,L13) such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers (M1) connected to circuitry. One or more upper metal layers (DO) are provided above the stack. Contact structures (2802...2814) extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures (2906, 2908) can connect the circuitry to the one or more upper metal layers.

Abstract translation: 为三维非易失性存储器件提供诸如电阻器和电容器的无源器件。 在基板的周边区域中，无源器件包括诸如氧化物和导电材料（L1，L3，...，L13）的电介质（L0，L2，...，L12）的交替层，例如重掺杂 堆叠中的多晶硅或金属硅化物。 衬底包括连接到电路的一个或多个下金属层（M1）。 在堆叠上方提供一个或多个上金属层（DO）。 接触结构（2802 ... 2814）从导电材料层延伸到一个或多个上金属层的部分，使得导电材料层彼此并联连接，用于电容器或串联连接，用于 电阻器，通过接触结构和至少一个上金属层。 附加接触结构（2906,2908）可以将电路连接到一个或多个上金属层。

公开(公告)号：WO2012067737A1

公开(公告)日：2012-05-24

申请号：PCT/US2011/056126

申请日：2011-10-13

Applicant: SANDISK 3D LLC ,  SAMACHISA, George ,  RABKIN, Peter ,  SCHEUERLEIN, Roy, E.

Inventor： SAMACHISA, George ,  RABKIN, Peter ,  SCHEUERLEIN, Roy, E.

IPC: G11C13/00

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72

Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

Abstract translation: 存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。 存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。 存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到 相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

公开(公告)号：WO2013078069A1

公开(公告)日：2013-05-30

申请号：PCT/US2012/065375

申请日：2012-11-15

Applicant: SANDISK TECHNOLOGIES, INC. ,  HIGASHITANI, Masaaki ,  RABKIN, Peter

Inventor： HIGASHITANI, Masaaki ,  RABKIN, Peter

IPC: H01L27/115 ,  H01L23/532

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/06 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked non-volatile memory cell array include cell areas (CA3,4) with rows of vertical columns of NAND cells, and an interconnect area (IA1), e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect (I1, I2) extending between insulation-filled slits (S5, S6, S7), and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.

Abstract translation: 堆叠的非易失性存储单元阵列包括具有NAND单元的垂直列行的单元区域（CA3,4），以及例如阵列中途并且延伸阵列的长度的互连区域（IA1）。 互连区域包括在绝缘填充的狭缝（S5，S6，S7）之间延伸的至少一个金属硅化物互连（I1，I2），并且不包括NAND单元的垂直列。 金属硅化物互连可以将电力和控制信号从堆叠下方传递到堆叠之上。 金属硅化物互连也可以形成在衬底的周边区域中。 接触结构可以从互连的梯形部分延伸到堆叠之上的至少一个上金属层，以完成从堆叠下方的电路到上金属层的导电路径。 可以在阵列的平面中提供子阵列，而不需要字线连接和子阵列之间的传输区域。

公开(公告)号：WO2011159583A3

公开(公告)日：2012-06-14

申请号：PCT/US2011040105

申请日：2011-06-10

Applicant: SANDISK 3D LLC ,  KREUPL FRANZ ,  BANDYOPADHYAY ABHIJIT ,  CHEN YUNG-TIN ,  FU CHU-CHEN ,  JAYASEKARA WIPUL PEMSIRI ,  KAI JAMES ,  MAKALA RAGHUVEER S ,  RABKIN PETER ,  SAMACHISA GEORGE ,  ZHANG JINGYAN

Inventor： KREUPL FRANZ ,  BANDYOPADHYAY ABHIJIT ,  CHEN YUNG-TIN ,  FU CHU-CHEN ,  JAYASEKARA WIPUL PEMSIRI ,  KAI JAMES ,  MAKALA RAGHUVEER S ,  RABKIN PETER ,  SAMACHISA GEORGE ,  ZHANG JINGYAN

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Abstract translation: 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

公开(公告)号：WO2011159583A2

公开(公告)日：2011-12-22

申请号：PCT/US2011/040105

申请日：2011-06-10

Applicant: SANDISK 3D LLC ,  KREUPL, Franz ,  BANDYOPADHYAY, Abhijit ,  CHEN, Yung-Tin ,  FU, Chu-Chen ,  JAYASEKARA, Wipul, Pemsiri ,  KAI, James ,  MAKALA, Raghuveer, S. ,  RABKIN, Peter ,  SAMACHISA, George ,  ZHANG, Jingyan

Inventor： KREUPL, Franz ,  BANDYOPADHYAY, Abhijit ,  CHEN, Yung-Tin ,  FU, Chu-Chen ,  JAYASEKARA, Wipul, Pemsiri ,  KAI, James ,  MAKALA, Raghuveer, S. ,  RABKIN, Peter ,  SAMACHISA, George ,  ZHANG, Jingyan

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Abstract translation: 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。