公开(公告)号：WO2018164742A1

公开(公告)日：2018-09-13

申请号：PCT/US2017/063075

申请日：2017-11-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： NORIZUKI, Naoto ,  OKIZUMI, Yasuchika ,  MADA, Shogo ,  OGAWA, Hiroyuki

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/11548 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.

公开(公告)号：WO2018128712A1

公开(公告)日：2018-07-12

申请号：PCT/US2017/060999

申请日：2017-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： GE, Chun ,  ZHANG, Yanli ,  ALSMEIER, Johann ,  YU, Fabo ,  YU, Jixin

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.

公开(公告)号：WO2018126256A2

公开(公告)日：2018-07-05

申请号：PCT/US2018/012022

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： LIU, Jun ,  HALLER, Gordon A. ,  WANG, Fei ,  NG, Wei Yeeng ,  MCKINSEY, Wesley O. ,  XIE, Zhiqiang ,  ADAMS, Jeremy F. ,  ZHU, Hongbin ,  ZHAO, Jun ,  LEVAN, Mark A.

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53214 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：WO2017142616A1

公开(公告)日：2017-08-24

申请号：PCT/US2016/067341

申请日：2016-12-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YU, Jixin ,  ZHANG, Yanli ,  LU, Zhenyu ,  ALSMEIER, Johann ,  MAO, Daxin

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11526

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42344

Abstract: A method of manufacturing a structure includes forming an alternating stack of insulating layers (42) and spacer material layers (32) over a substrate (9), dividing the alternating stack into a first alternating stack (100, 300) and a second alternating stack (200), the first alternating stack having first stepped surfaces and the second alternating stack having second stepped surfaces, forming at least one memory stack structure through the first alternating stack (100), each of the at least one memory stack structure including charge storage regions, a tunneling dielectric, and a semiconductor channel, replacing portions of the insulating layers in the first alternating stack with electrically conductive layers (46) while leaving intact portions of the insulating layers (42) in the second alternating stack, and forming a contact via structure (84) through the second alternating stack to contact a peripheral semiconductor device under the second stack.

Abstract translation: 制造结构的方法包括在衬底（9）上方形成绝缘层（42）和间隔材料层（32）的交替叠层，将交替叠层分成第一交替叠层（100 ，300）和第二交替堆叠（200），所述第一交替堆叠具有第一阶梯式表面并且所述第二交替堆叠具有第二阶式表面，形成穿过所述第一交替堆叠（100）的至少一个存储器堆叠结构，所述at 至少一个存储器堆叠结构，包括电荷存储区域，隧穿电介质和半导体沟道，用导电层（46）替换第一交替堆叠中的绝缘层的部分，同时使绝缘层（42）的完整部分留在 第二交替堆叠，并且形成穿过第二交替堆叠的接触过孔结构（84）以接触第二堆叠下的外围半导体器件。

公开(公告)号：WO2016170759A1

公开(公告)日：2016-10-27

申请号：PCT/JP2016/002025

申请日：2016-04-14

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： SUMINO, Jun

IPC: H01L27/115 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L45/16 ,  H01L21/768 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.

Abstract translation: 提供配置为有效使用区域的套接字结构，以及提供有效使用区域的插座区域的方法。 楼梯型接触区域或插座区域包括相邻平面电极之间的电介质层，其部分地覆盖直接位于相邻平面电极下面的平面电极的一部分。 相邻平面电极之间的电介质层的部分可以是倾斜的，使得其从上覆平面电极的边缘延伸到下面的平面电极的边缘与对应于上覆平面电极的边缘的点之间的点。

公开(公告)号：WO2016170758A1

公开(公告)日：2016-10-27

申请号：PCT/JP2016/002024

申请日：2016-04-14

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： SUMINO, Jun

IPC: H01L27/115

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.

Abstract translation: 提供被配置为有效使用区域的三维存储器结构以及用于提供有效使用区域的三维存储器结构的方法。 垂直存储器结构可以包括大于字线位数的多个位线位。 此外，位线位与字线位的比例可以等于包含在存储器结构的存储器阵列中的存储单元的第一侧与存储器单元的第二侧的尺寸之比。

公开(公告)号：WO2016167984A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/025394

申请日：2016-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  KOKA, Sateesh ,  KUBO, Tomohiro ,  ARIYOSHI, Junichi ,  MATAMIS, George

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material. The vertical semiconductor channel can be formed in a single deposition process, thereby eliminating any interface therein and minimizing the resistance of the vertical semiconductor channel.

Abstract translation: 通过在位于衬底内的垂直半导体沟道和水平半导体沟道之间形成金属 - 半导体合金区域，可以减少三维存储堆叠结构中的半导体沟道的电阻。 金属 - 半导体合金区域可以通过在形成记忆膜之后在存储器开口下面的半导体衬底中的一部分半导体材料层凹陷来形成，在凹陷区域中选择性地沉积金属材料，沉积垂直半导体沟道，以及 使沉积的金属材料与半导体材料层和垂直半导体沟道的相邻部分反应。 在金属材料的选择性沉积之前，可以在记忆膜上形成牺牲介电材料层。 可以在单个沉积工艺中形成垂直半导体沟道，从而消除其中的任何界面并使垂直半导体沟道的电阻最小化。

公开(公告)号：WO2016126305A1

公开(公告)日：2016-08-11

申请号：PCT/US2015/062194

申请日：2015-11-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YADA, Shinsuke ,  OGAWA, Hiroyuki

IPC: H01L27/115

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract translation: 三维NAND器件包括与第一阶梯式字线接触区域中的各个奇数字线的接触部分接触的第一组字线触点，以及与第二组字线触点接触的第二组字线触点， 在第二阶梯式字线接触区域中的各个偶数字线。 第一字线接触区域中的偶数字线不接触字线接触，而第二字线接触区域中的奇数字线不接触字线接触。

公开(公告)号：WO2016060012A1

公开(公告)日：2016-04-21

申请号：PCT/JP2015/078334

申请日：2015-10-06

Applicant: 株式会社フローディア

Inventor： 谷口　泰弘 ,  川嶋　泰彦 ,  葛西　秀男 ,  櫻井　良多郎 ,  品川　裕 ,  奥山　幸祐

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11575 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/7881

Abstract: 　周辺回路領域（ER2）のロジックゲート電極（G5,G6）を形成するフォトマスク工程の際に、同時にメモリ回路領域（ER1）の周回導電層（Ga,Gb）も分断して、電気的に分離した第1選択ゲート電極（G2a,G2b）および第2選択ゲート電極（G3a,G3b）を形成できることから、独立して制御可能な第1選択ゲート電極（G2a,G2b）および第2選択ゲート電極（G3a,G3b）を形成する場合でも、従来のメモリ回路領域だけを加工する専用フォトマスク工程に加えて、さらにメモリ回路領域（ER1）だけを加工する専用フォトマスク工程を余分に追加する必要がなく、その分、製造コストを低減できる、半導体集積回路装置の製造方法、および半導体集積回路装置を提案する。

Abstract translation: 提供了一种用于制造半导体集成电路器件的方法，在用于在外围电路区域（ER2）中形成逻辑栅电极（G5，G6）的光掩模步骤期间，能够将围绕导电层（Ga，Gb） 存储电路区域（ER1），以形成电分离的第一选择栅电极（G2a，G2b）和第二选择栅电极（G3a，G3b）。 因此，即使在形成第一选择栅电极（G2a）的情况下，仅需要存储电路区域（ER1）的仅用于处理存储电路区域（ER1）的额外的专用光掩模步骤也不需要进一步添加到用于仅处理存储电路区域的常规专用光掩模步骤 ，G2b）和能够独立控制的第二选择栅电极（G3a，G3b），从而可以降低生产成本。 还提供了一种半导体集成电路器件。

公开(公告)号：WO2015126664A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/015155

申请日：2015-02-10

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： PACHAMUTHU, Jayavel ,  ALSMEIER, Johann ,  CHIEN, Henry

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L29/7926

Abstract: A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.

Abstract translation: 包括第一导电层和第一电绝缘层的交替层的第一叠层形成有第一台阶表面和其上的第一介电材料部分。 可以通过第一台阶表面形成包括电介质金属氧化物的介质柱结构。 可以形成下部存储器开口，并且填充有包括下部半导体沟道和掺杂半导体区域的一次性材料或下部存储器开口结构。 可以顺序地形成至少一个介电材料层和包括第二导电层和第二电绝缘层的交替层的第二堆叠。 上存储器开口可以通过第二堆叠和至少一个电介质材料层形成。 可以在去除一次性材料之后形成记忆膜和半导体通道，或者可以在掺杂半导体区域上形成上半导体沟道。