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    LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING
    2.
    发明申请
    LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING 审中-公开
    具有增强离子化和射频功率耦合的低电阻TUNGSTEN PVD

    公开(公告)号：WO2011156650A2

    公开(公告)日：2011-12-15

    申请号：PCT/US2011/039867

    申请日：2011-06-09

    Applicant: APPLIED MATERIALS, INC. ,  CAO, Yong ,  TANG, Xianmin ,  GANDIKOTA, Srinivas ,  WANG, Wei D. ,  LIU, Zhendong ,  MORAES, Kevin ,  RASHEED, Muhammad M. ,  NGUYEN, Thanh X. ,  JUPUDI, Ananthkrishna

    Inventor： CAO, Yong ,  TANG, Xianmin ,  GANDIKOTA, Srinivas ,  WANG, Wei D. ,  LIU, Zhendong ,  MORAES, Kevin ,  RASHEED, Muhammad M. ,  NGUYEN, Thanh X. ,  JUPUDI, Ananthkrishna

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/43

    CPC classification number: H01L21/28079 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/28088 ,  H01L21/2855 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

    Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal nitride film layer on the conductive film layer, a silicon-containing film layer on the refractory metal nitride film layer, and a tungsten film layer on the silicon-containing film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

    Abstract translation: 本文描述的实施例提供了一种半导体器件及其形成方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 栅极电极堆叠包括在栅极电介质层上的导电膜层，导电膜层上的难熔金属氮化物膜层，难熔金属氮化物膜层上的含硅膜层，以及硅 - 含有膜层。 在一个实施例中，该方法包括将衬底定位在处理室内，其中衬底包括源极和漏极区域，源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化物膜层，在难熔金属氮化物膜层上沉积含硅膜层，并在含硅膜层上沉积钨膜层。

    SURFACE TREATED ALUMINUM NITRIDE BAFFLE
    3.
    发明申请
    SURFACE TREATED ALUMINUM NITRIDE BAFFLE 审中-公开
    表面处理的硝酸铝

    公开(公告)号：WO2010022212A3

    公开(公告)日：2010-05-14

    申请号：PCT/US2009054416

    申请日：2009-08-20

    Applicant: APPLIED MATERIALS INC ,  RASHEED MUHAMMAD M ,  LUBOMIRSKY DMITRY

    Inventor： RASHEED MUHAMMAD M ,  LUBOMIRSKY DMITRY

    IPC: H01L21/205 ,  H01L21/00

    CPC classification number: C23C16/45591 ,  C04B35/581 ,  C04B40/0092 ,  C23C16/4404 ,  C23C16/45563 ,  C23C16/45565 ,  H01J37/32449 ,  H01L21/02271 ,  H01L21/0262 ,  H01L21/28556

    Abstract: Methods and apparatus relating to aluminum nitride baffles are provided herein. In some embodiments, a baffle for use in semiconductor process chambers may include a body comprising aluminum nitride and a metal oxide binding agent, wherein a ratio of aluminum nitride to metal oxide on a surface of the body is greater than or equal to the ratio within the body. In some embodiments, the body may have a center stem and an outer annulus coupled to and extending radially outwards from a lower portion of the center stem. In some embodiments, a method of fabricating a baffle may include sintering aluminum, nitrogen, and a metal oxide binding agent to form a body of the baffle, the body having excess metal oxide binding agent disposed on a surface thereof; and removing a bulk of the excess metal oxide binding agent from a surface of the body.

    Abstract translation: 本文提供了与氮化铝挡板相关的方法和装置。 在一些实施例中，用于半导体处理腔室的挡板可以包括包括氮化铝和金属氧化物结合剂的主体，其中，主体表面上的氮化铝与金属氧化物的比例大于或等于 身体。 在一些实施例中，主体可以具有中心杆和外环，其与中心杆的下部连接并径向向外延伸。 在一些实施例中，制造挡板的方法可以包括烧结铝，氮和金属氧化物结合剂以形成挡板的主体，该主体具有设置在其表面上的多余的金属氧化物粘合剂; 以及从身体的表面去除大量的多余的金属氧化物粘合剂。

    LOW PROFILE PROCESS KIT
    4.
    发明申请
    LOW PROFILE PROCESS KIT 审中-公开
    低配置工艺包

    公开(公告)号：WO2009132181A2

    公开(公告)日：2009-10-29

    申请号：PCT/US2009/041528

    申请日：2009-04-23

    Applicant: APPLIED MATERIALS, INC. ,  RASHEED, Muhammad, M. ,  IWASHITA, Teruki ,  OTAKE, Hiroshi ,  KOGA, Yuki ,  MAEHARA, Kazutoshi ,  CHEN, Xinglong ,  GONDHALEKAR, Sudhir ,  LUBOMIRSKY, Dmitry

    Inventor： RASHEED, Muhammad, M. ,  IWASHITA, Teruki ,  OTAKE, Hiroshi ,  KOGA, Yuki ,  MAEHARA, Kazutoshi ,  CHEN, Xinglong ,  GONDHALEKAR, Sudhir ,  LUBOMIRSKY, Dmitry

    IPC: H01L21/683 ,  H01L21/687

    CPC classification number: C23C16/4585 ,  C23C16/4581 ,  H01J37/32082 ,  H01J37/32642 ,  H01L21/68735

    Abstract: Embodiments of process kits for substrate supports of semiconductor substrate process chambers are provided herein. In some embodiments, a process kit for a semiconductor process chamber may include an annular body being substantially horizontal and having an inner and an outer edge, and an upper and a lower surface; an inner lip disposed proximate the inner edge and extending vertically from the upper surface; and an outer lip disposed proximate the outer edge and on the lower surface, and having a shape conforming to a surface of the substrate support pedestal. In some embodiments, a process kit for a semiconductor process chamber my include an annular body having an inner and an outer edge, and having an upper and lower surface, the upper surface disposed at a downward angle of between about 5-65 degrees in a radially outward direction from the inner edge toward the outer edge.

    Abstract translation: 本文提供了半导体衬底处理室的衬底支撑件的工艺组件的实施例。 在一些实施例中，用于半导体处理室的处理套件可以包括基本上水平的并具有内部和外部边缘以及上部和下部表面的环形体; 靠近所述内边缘并从所述上表面垂直延伸的内唇缘; 以及设置在所述外边缘和所述下表面附近并且具有与所述基板支撑基座的表面相符的形状的外唇缘。 在一些实施例中，用于半导体处理室my的处理套件包括具有内边缘和外边缘的环形体，并且具有上表面和下表面，上表面以约5-65度的向下角度设置在 从内缘朝向外缘的径向向外方向。

    PVD SPUTTERING TARGET WITH A PROTECTED BACKING PLATE
    6.
    发明申请
    PVD SPUTTERING TARGET WITH A PROTECTED BACKING PLATE 审中-公开
    带有保护背板的PVD溅射目标

    公开(公告)号：WO2012109069A3

    公开(公告)日：2013-01-03

    申请号：PCT/US2012023474

    申请日：2012-02-01

    Applicant: APPLIED MATERIALS INC ,  RASHEED MUHAMMAD M ,  WANG RONGJUN

    Inventor： RASHEED MUHAMMAD M ,  WANG RONGJUN

    IPC: C23C14/34 ,  C23C14/50

    CPC classification number: C23C14/3407 ,  C22C9/00 ,  C22C9/04 ,  C22C19/03 ,  C23C14/3414 ,  H01J37/3426 ,  H01J37/3435

    Abstract: Embodiments of the invention provide sputtering targets utilized in physical vapor deposition (PVD) and methods to form such sputtering targets. In one embodiment, a sputtering target contains a target layer disposed on a backing plate, and a protective coating layer - usually containing a nickel material - covering and protecting a region of the backing plate that would otherwise be exposed to plasma during the PVD processes. In many examples, the target layer contains a nickel-platinum alloy, the backing plate contains a copper alloy (e.g., copper-zinc), and the protective coating layer contains metallic nickel. The protective coating layer eliminates the formation of highly conductive, copper contaminants typically derived by plasma erosion of the copper alloy contained within the exposed surfaces of the backing plate. Therefore, the substrates and the interior surfaces of the PVD chamber remain free of such copper contaminants during the PVD processes.

    Abstract translation: 本发明的实施例提供了用于物理气相沉积（PVD）的溅射靶和形成这种溅射靶的方法。 在一个实施例中，溅射靶包含设置在背板上的目标层和通常包含镍材料的保护涂层 - 覆盖并保护背衬板的区域，否则在PVD工艺期间将暴露于等离子体。 在许多实施例中，靶层含有镍 - 铂合金，背板含有铜合金（例如铜 - 锌），保护涂层含有金属镍。 保护涂层消除了形成高度导电的铜污染物，通常由包含在背板的暴露表面内的铜合金的等离子体侵蚀导致。 因此，在PVD工艺期间，PVD室的基板和内表面保持没有这种铜污染物。

    PROCESS KIT FOR RF PHYSICAL VAPOR DEPOSITION
    8.
    发明申请
    PROCESS KIT FOR RF PHYSICAL VAPOR DEPOSITION 审中-公开
    RF物理蒸气沉积工艺套件

    公开(公告)号：WO2011019566A2

    公开(公告)日：2011-02-17

    申请号：PCT/US2010/044420

    申请日：2010-08-04

    Applicant: APPLIED MATERIALS, INC. ,  HAWRYLCHAK, Lara ,  SAVANDAIAH, Kirankumar ,  RASHEED, Muhammad, M. ,  WANG, Rongjun ,  ALLEN, Adolph, Miller ,  XIE, Zhigang

    Inventor： HAWRYLCHAK, Lara ,  SAVANDAIAH, Kirankumar ,  RASHEED, Muhammad, M. ,  WANG, Rongjun ,  ALLEN, Adolph, Miller ,  XIE, Zhigang

    IPC: H01L21/203 ,  C23C14/34

    CPC classification number: H01L21/67017 ,  C23C14/34 ,  C23C14/564 ,  H01J37/3408 ,  H01J37/3447

    Abstract: Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a cover ring, a shield, and an isolator for use in a physical deposition chamber. The components of the process kit work alone and in combination to significantly reduce particle generation and stray plasmas. In comparison with existing multiple part shields, which provide an extended RF return path contributing to RF harmonics causing stray plasma outside the process cavity, the components of the process kit reduce the RF return path thus providing improved plasma containment in the interior processing region.

    Abstract translation: 本发明的实施例一般涉及用于半导体处理室的处理套件和具有套件的半导体处理室。 更具体地，本文所述的实施例涉及包括用于物理沉积室中的盖环，屏蔽和隔离器的处理套件。 过程组件的组件单独工作并组合起来，以显着减少颗粒产生和杂散等离子体。 与现有的多部分屏蔽相比，其提供了有助于RF谐波的扩展的RF返回路径，从而在处理空腔之外引起杂散等离子体，处理套件的部件降低了RF返回路径，从而在内部处理区域中提供了改进的等离子体容纳物。

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