公开(公告)号：WO2008042843A2

公开(公告)日：2008-04-10

申请号：PCT/US2007080069

申请日：2007-10-01

Applicant: FAIRCHILD SEMICONDUCTOR ,  CALAFUT DANIEL S ,  YILMAZ HAMZA ,  SAPP STEVEN

Inventor： CALAFUT DANIEL S ,  YILMAZ HAMZA ,  SAPP STEVEN

IPC: H01L27/06

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L29/7808 ,  H01L2924/0002 ,  H03K17/08122 ,  H03K17/0822 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

Abstract translation: 用于功率MOSFET的静电放电（ESD）保护网络包括并联支路，其包含多晶硅齐纳二极管和电阻器，用于保护栅极免受由ESD引起的高压引起的破坏。 分支可以具有相同或独立的路径，用于电压跨越栅极区域进入半导体衬底。 具体地，次级分支具有比主分支更高的击穿电压，使得电压在保护网络的两个分支上共享。 器件的ESD保护网络提供了更有效的设计，而不增加芯片上使用的空间。 ESD保护网络还可以与其他有源和无源器件如晶闸管，绝缘栅双极晶体管和双极结型晶体管一起使用。

公开(公告)号：WO2005065385A3

公开(公告)日：2005-07-21

申请号：PCT/US2004/043965

申请日：2004-12-29

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  CHALLA, Ashok ,  ELBANHAWY, Alan ,  GREBS, Thomas E. ,  KOCON, Christopher B. ,  KRAFT, Nathan L. ,  PROBST, Dean E. ,  RIDLEY, Rodney S. ,  SAPP, Steven P. ,  WANG, Qi ,  WILSON, Peter H. ,  YEDINAK, Joseph A. ,  YUN, Chongman ,  JUNG, Jin-young ,  JANG, Ho-cheol ,  STOKES, Richard ,  DOLNY, Gary M. ,  MYTYCH, John ,  LOSEE, Becky ,  SELSLEY, Adam ,  HERRICK, Robert ,  MURPHY, James J. ,  MADSON, Gordon K. ,  WOOLSEY, Debra S. ,  MARCHANT, Bruce D. ,  REXER, Christopher L ,  SANI, Babak S. ,  LEE, Jae-Gil

Inventor： CHALLA, Ashok ,  ELBANHAWY, Alan ,  GREBS, Thomas E. ,  KOCON, Christopher B. ,  KRAFT, Nathan L. ,  PROBST, Dean E. ,  RIDLEY, Rodney S. ,  SAPP, Steven P. ,  WANG, Qi ,  WILSON, Peter H. ,  YEDINAK, Joseph A. ,  YUN, Chongman ,  JUNG, Jin-young ,  JANG, Ho-cheol ,  STOKES, Richard ,  DOLNY, Gary M. ,  MYTYCH, John ,  LOSEE, Becky ,  SELSLEY, Adam ,  HERRICK, Robert ,  MURPHY, James J. ,  MADSON, Gordon K. ,  WOOLSEY, Debra S. ,  MARCHANT, Bruce D. ,  REXER, Christopher L ,  SANI, Babak S. ,  LEE, Jae-Gil

IPC: H01L29/78

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronics are disclosed. One aspect of the invention combines a number of charge balancing techniques (311) and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices (300B) with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices (300B) are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches (300, 302), formation of dielectric layers inside trenches (301, 302), formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices (300B) incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device (300B) and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：WO2006135746A2

公开(公告)日：2006-12-21

申请号：PCT/US2006/022474

申请日：2006-06-08

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  YILMAZ, Hamza ,  CALAFUT, Daniel ,  SAPP, Steven, P. ,  KRAFT, Nathan ,  CHALLA, Ashok

Inventor： YILMAZ, Hamza ,  CALAFUT, Daniel ,  SAPP, Steven, P. ,  KRAFT, Nathan ,  CHALLA, Ashok

IPC: H01L21/8242

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

Abstract translation: 场效应晶体管如下形成。 提供了具有在半导体区域上延伸的具有第二导电性的外延层的第一导电类型的半导体区域。 形成延伸穿过外延层并终止在半导体区域中的沟槽。 执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。 执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。 形成沟槽每一侧的第一导电类型的源区。

公开(公告)号：WO2006108011A2

公开(公告)日：2006-10-12

申请号：PCT/US2006/012581

申请日：2006-04-04

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  KOCON, Christopher, Boguslaw ,  SAPP, Steven, P. ,  THORUP, Paul ,  PROBST, Dean, E. ,  HERRICK, Robert ,  LOSEE, Becky ,  YILMAZ, Hamza ,  REXER, Christopher, Lawrence ,  CALAFUT, Daniel

Inventor： KOCON, Christopher, Boguslaw ,  SAPP, Steven, P. ,  THORUP, Paul ,  PROBST, Dean, E. ,  HERRICK, Robert ,  LOSEE, Becky ,  YILMAZ, Hamza ,  REXER, Christopher, Lawrence ,  CALAFUT, Daniel

IPC: H01L29/94 ,  H01L21/8242

CPC classification number: H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

Abstract: A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape clank each side of the gate trenches. A contact opening extends into the semiconductor regions between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at leaset a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.

Abstract translation: 单片集成场效应晶体管和肖特基二极管包括延伸到半导体区域的栅极沟槽。 具有大致三角形形状的源极区域跨越栅极沟槽的每一侧。 接触开口延伸到相邻栅极沟槽之间的半导体区域。 导体层填充接触开口以电接触：（a）源区域沿着每个源极区域的倾斜侧壁的一部分，以及（b）沿接触开口底部的半导体区域，其中导体 层与半导体区形成肖特基接触。

公开(公告)号：WO2010144375A2

公开(公告)日：2010-12-16

申请号：PCT/US2010/037656

申请日：2010-06-07

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  KIM, Suku ,  CALAFUT, Dan ,  HO, Ihsiu ,  KINZER, Dan ,  SAPP, Steven ,  CHALLA, Ashok ,  JO, Seokjin ,  LARSEN, Mark

Inventor： KIM, Suku ,  CALAFUT, Dan ,  HO, Ihsiu ,  KINZER, Dan ,  SAPP, Steven ,  CHALLA, Ashok ,  JO, Seokjin ,  LARSEN, Mark

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4933

Abstract: Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Abstract translation: 描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近 源区。 因此，在主线状沟槽内形成较小的支柱沟槽。 这种架构产生基本垂直于常规线形通道排列的附加通道区域。 常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。 通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。 描述其他实施例。

公开(公告)号：WO2007117844A3

公开(公告)日：2008-04-17

申请号：PCT/US2007063903

申请日：2007-03-13

Applicant: FAIRCHILD SEMICONDUCTOR ,  YILMAZ HAMZA ,  SAPP STEVEN ,  WANG QI ,  LI MINHUA ,  MURPHY JAMES J ,  DIROLL JOHN ROBERT

Inventor： YILMAZ HAMZA ,  SAPP STEVEN ,  WANG QI ,  LI MINHUA ,  MURPHY JAMES J ,  DIROLL JOHN ROBERT

IPC: H01L23/48 ,  H01L21/31

CPC classification number: H01L23/3114 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L25/072 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Abstract translation: 公开了一种半导体管芯封装。 半导体管芯封装包括金属基板和半导体管芯，其包括第一表面，第一表面包括第一电端子，第二表面，包括第二电端子和至少一个孔。 金属基板附接到第二表面。 多个导电结构在半导体管芯上，并且包括设置在该至少一个孔中的至少一个导电结构。 其他导电结构可以设置在半导体管芯的第一表面上。

公开(公告)号：WO2008042843A3

公开(公告)日：2008-04-10

申请号：PCT/US2007/080069

申请日：2007-10-01

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  CALAFUT, Daniel, S. ,  YILMAZ, Hamza ,  SAPP, Steven

Inventor： CALAFUT, Daniel, S. ,  YILMAZ, Hamza ,  SAPP, Steven

IPC: H01L29/68

Abstract: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

公开(公告)号：WO2006127914A2

公开(公告)日：2006-11-30

申请号：PCT/US2006/020274

申请日：2006-05-24

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  YILMAZ, Hamza ,  CALAFUT, Daniel ,  KOCON, Christopher, Boguslaw ,  SAPP, Steven, P. ,  PROBST, Dean, E. ,  KRAFT, Nathan, L. ,  GREBS, Thomas, E. ,  RIDLEY, Rodney, S. ,  DOLNY, Gary, M. ,  MARCHANT, Bruce, D. ,  YEDINAK, Joseph, A.

Inventor： YILMAZ, Hamza ,  CALAFUT, Daniel ,  KOCON, Christopher, Boguslaw ,  SAPP, Steven, P. ,  PROBST, Dean, E. ,  KRAFT, Nathan, L. ,  GREBS, Thomas, E. ,  RIDLEY, Rodney, S. ,  DOLNY, Gary, M. ,  MARCHANT, Bruce, D. ,  YEDINAK, Joseph, A.

IPC: H01L29/94

CPC classification number: H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Abstract translation: 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 至少一个导电屏蔽电极设置在栅极沟槽中。 栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。 屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。 栅极电介质层使栅电极与体区绝缘。 屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

公开(公告)号：WO2010144375A3

公开(公告)日：2011-03-03

申请号：PCT/US2010037656

申请日：2010-06-07

Applicant: FAIRCHILD SEMICONDUCTOR ,  KIM SUKU ,  CALAFUT DAN ,  HO IHSIU ,  KINZER DAN ,  SAPP STEVEN ,  CHALLA ASHOK ,  JO SEOKJIN ,  LARSEN MARK

Inventor： KIM SUKU ,  CALAFUT DAN ,  HO IHSIU ,  KINZER DAN ,  SAPP STEVEN ,  CHALLA ASHOK ,  JO SEOKJIN ,  LARSEN MARK

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4933

Abstract: Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Abstract translation: 描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近 源区。 因此，在主线状沟槽内形成较小的支柱沟槽。 这种架构产生基本垂直于常规线形通道排列的附加通道区域。 常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。 通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。 描述其他实施例。

公开(公告)号：WO2008147437A1

公开(公告)日：2008-12-04

申请号：PCT/US2007/081554

申请日：2007-10-16

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  KRAFT, Nathan, L. ,  CHALLA, Ashok ,  SAPP, Steven, P. ,  YILMAZ, Hamza ,  CALAFUT, Daniel ,  PROBST, Dean, E. ,  RIDLEY, Rodney, S. ,  GREBS, Thomas, E. ,  KOCON, Christopher, B. ,  YEDINAK, Joseph, A. ,  DOLNY, Gary, M.

Inventor： KRAFT, Nathan, L. ,  CHALLA, Ashok ,  SAPP, Steven, P. ,  YILMAZ, Hamza ,  CALAFUT, Daniel ,  PROBST, Dean, E. ,  RIDLEY, Rodney, S. ,  GREBS, Thomas, E. ,  KOCON, Christopher, B. ,  YEDINAK, Joseph, A. ,  DOLNY, Gary, M.

IPC: H01L21/8242

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

Abstract translation: 场效应晶体管如下形成。 沟槽形成在第一导电类型的半导体区域中。 每个沟槽部分地填充有一种或多种材料。 执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。 进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻沟槽之间形成第二导电类型的体区。 然后在每个身体区域中形成第一导电类型的源区域。