公开(公告)号：WO2012087578A3

公开(公告)日：2012-06-28

申请号：PCT/US2011/063778

申请日：2011-12-07

Applicant: INTEL CORPORATION ,  SIMKA, Harsono S. ,  ZIERATH, Daniel J. ,  HAVERTY, Michael G. ,  SHANKAR, Sadasivan

Inventor： SIMKA, Harsono S. ,  ZIERATH, Daniel J. ,  HAVERTY, Michael G. ,  SHANKAR, Sadasivan

IPC: H01L21/28 ,  H01L21/31

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

公开(公告)号：WO2015147843A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/032073

申请日：2014-03-27

Applicant: INTEL CORPORATION ,  BLACKWELL, James M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  KLOSTER, Grant M. ,  GSTREIN, Florian ,  SIMKA, Harsono S. ,  ZIMMERMAN, Paul A. ,  BRISTOL, Robert L.

Inventor： BLACKWELL, James M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  KLOSTER, Grant M. ,  GSTREIN, Florian ,  SIMKA, Harsono S. ,  ZIMMERMAN, Paul A. ,  BRISTOL, Robert L.

IPC: C23C16/455 ,  C23C16/52 ,  H01L21/285

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract translation: 描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。 在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。 该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

公开(公告)号：WO2012087578A2

公开(公告)日：2012-06-28

申请号：PCT/US2011063778

申请日：2011-12-07

Applicant: INTEL CORP ,  SIMKA HARSONO S ,  ZIERATH DANIEL J ,  HAVERTY MICHAEL G ,  SHANKAR SADASIVAN

Inventor： SIMKA HARSONO S ,  ZIERATH DANIEL J ,  HAVERTY MICHAEL G ,  SHANKAR SADASIVAN

IPC: H01L21/28 ,  H01L21/31

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

Abstract translation: 提供了用于集成电路的电互连和制造互连的方法。 提供了包括铜互连件的装置，其具有包含银和第二成分（诸如镧，钛，钨，锆，锑或钙）的金属衬里层。 方法包括提供具有在其中形成的沟槽或通孔的衬底，在特征的表面上形成银合金层，其包含银和选自镧，钛，钨，锆，锑和钙的第二组分， 沉积铜种子层，并将铜沉积到特征中。