公开(公告)号：WO2013032906A1

公开(公告)日：2013-03-07

申请号：PCT/US2012/052271

申请日：2012-08-24

Applicant: EFFICIENT POWER CONVERSION CORPORATION ,  DE ROOIJ, Michael, A. ,  STRYDOM, Johan

Inventor： DE ROOIJ, Michael, A. ,  STRYDOM, Johan

IPC: H03K17/56

CPC classification number: H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H03K17/122

Abstract: Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.

Abstract translation: 并联晶体管电路具有从普通源极感应效应降低的效果。 并联晶体管包括物理栅极连接，这些物理栅极连接彼此电气靠近。 并联电路被布置成使得由跨过公共源电感的瞬态电流产生的公共栅极连接处的电压基本上是平衡的。 电路包括开关电路，转换器和RF放大器。

公开(公告)号：WO2012082840A1

公开(公告)日：2012-06-21

申请号：PCT/US2011/064803

申请日：2011-12-14

Applicant: EFFICIENT POWER CONVERSION CORPORATION ,  LIDOW, Alexander ,  CAO, Jianjun ,  BEACH, Robert ,  STRYDOM, Johan ,  NAKATA, Alana ,  ZHAO, Guang, Yuan

Inventor： LIDOW, Alexander ,  CAO, Jianjun ,  BEACH, Robert ,  STRYDOM, Johan ,  NAKATA, Alana ,  ZHAO, Guang, Yuan

IPC: H01L21/337

CPC classification number: H01L21/743 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/732 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7827 ,  H01L29/88 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract translation: 用于将半导体器件的一部分中的周围材料独立地连接到其相应器件的触点的电路，结构和技术。 为了实现这一点，提供了以至少一个偏置极性电隔离的一个或多个导电阱的组合。

公开(公告)号：WO2008019122A3

公开(公告)日：2008-12-18

申请号：PCT/US2007017460

申请日：2007-08-06

Applicant: INT RECTIFIER CORP ,  STRYDOM JOHAN TJEERD ,  HONDA JUN

Inventor： STRYDOM JOHAN TJEERD ,  HONDA JUN

IPC: H03F3/217

CPC classification number: H03F3/217 ,  H03F1/305

Abstract: A method of minimizing an audible click noise from a speaker in a Class D audio power amplifier upon shutdown or startup of a switching stage having two switches series connected at a node, the speaker being connected to the node via an output filter comprising an inductor and a capacitor, the switches being controlled by a controller. The method including the steps of determining a timing interval at the node to transition a peak voltage of the capacitor, the capacitor voltage being a speaker voltage; and eliminating the audible transient voltage excursion across the speaker that causes a click noise during the timing interval, wherein at startup ON and OFF times of the switches are incrementally increased from zero to a normal mode and at shutdown the ON OFF times of the switches are incrementally decreased from the normal mode to zero.

Abstract translation: 一种在关闭或启动具有在节点处连接的两个开关串联的开关级的情况下使来自D类音频功率放大器的扬声器的可听咔嗒声噪声最小化的方法，所述扬声器经由包括电感器的输出滤波器连接到所述节点， 电容器，开关由控制器控制。 该方法包括以下步骤：确定节点处的时间间隔以转变电容器的峰值电压，电容器电压为扬声器电压; 并且消除扬声器周围的可听到的瞬态电压偏移，在定时间隔期间引起咔嗒声，其中在开关的启动时，ON和OFF时间从零增加到正常模式，并且在关闭时，开关的ON OFF时间是 从正常模式逐渐减少到零。

公开(公告)号：WO2013188119A1

公开(公告)日：2013-12-19

申请号：PCT/US2013/043315

申请日：2013-05-30

Applicant: EFFICIENT POWER CONVERSION CORPORATION ,  DE ROOIJ, Michael, Andrew ,  STRYDOM, Johan

Inventor： DE ROOIJ, Michael, Andrew ,  STRYDOM, Johan

IPC: G05F1/70

CPC classification number: H02M1/4208 ,  H02M1/4225 ,  H02M1/4233 ,  H02M3/1588 ,  Y02B70/126 ,  Y02B70/1466

Abstract: A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as "predictive diode emulation" to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes.

Abstract translation: 功率因数校正（PFC）升压电路。 PFC升压电路可以包括第一开关装置，第二开关装置，耦合到第一开关装置的第一栅极驱动器，耦合到第二开关装置的第二栅极驱动器和被配置为控制第一和第二栅极的PFC控制器 驱动程序。 PFC控制器将利用一种新技术，这里称为“预测二极管仿真”，以期望的方式控制开关器件，并克服使用传统二极管仿真可能出现的低效率和其他问题。 PFC控制器配置为在同步和非同步模式下工作。

公开(公告)号：WO0237729A3

公开(公告)日：2002-12-05

申请号：PCT/IB0102076

申请日：2001-11-06

Applicant: ONSHELF TRADING NINETY SEVEN P ,  STRYDOM JOHAN LAMPRECHT THERON ,  OOSTHUIZEN DAVID THOMAS ,  POPOVIC LIDIJA ,  EHLERS LIESL ,  GROBLER JOHAN THEODORUS ,  MOSS ANTONY

Inventor： STRYDOM JOHAN LAMPRECHT THERON ,  OOSTHUIZEN DAVID THOMAS ,  POPOVIC LIDIJA ,  EHLERS LIESL ,  GROBLER JOHAN THEODORUS ,  MOSS ANTONY

IPC: G06Q20/00 ,  G06Q30/00 ,  H04L29/06 ,  H04L29/08 ,  G06F17/60

CPC classification number: H04L67/20 ,  G06Q20/04 ,  G06Q20/10 ,  G06Q20/102 ,  G06Q20/12 ,  G06Q20/20 ,  G06Q20/202 ,  G06Q20/24 ,  G06Q30/06 ,  H04L29/06 ,  H04L69/16 ,  H04L69/163 ,  H04L69/329

Abstract: A web-based processing system providing subscribers with a facility to open an Internet bank directly, an online shopping facility and various other services. The system includes a central computing facility including a transaction manager server (12) and a client administration system (CAS) server (14), which are connected to banking servers (16) and (18) of a banking institution (20). The transaction manager (12) is connected to various merchants, via an online shopping facility (22) and a plurality of different e-commerce websites (24). The server (14) handles client interfaces, whereas the server (12) interfaces with banking servers and online shopping facility (12) and the e-commerce websites (24). The transaction manager handles all transactions and external communications between the various servers. The central computing facility monitors data processing carried out between remote client devices and the merchants and the banking institution and records the data in a client administration database.

Abstract translation: 基于网络的处理系统为用户提供直接开设互联网银行的设施，网上购物设施和各种其他服务。 该系统包括连接到银行机构（20）的银行服务器（16）和（18）的包括交易管理服务器（12）和客户管理系统（CAS）服务器（14）的中央计算设施。 交易管理器（12）通过在线购物设施（22）和多个不同的电子商务网站（24）连接到各种商家。 服务器（14）处理客户端接口，而服务器（12）与银行服务器和在线购物设施（12）以及电子商务网站（24）连接。 事务管理器处理各种服务器之间的所有事务和外部通信。 中央计算设备监视在远程客户端设备与商家和银行机构之间进行的数据处理，并将数据记录在客户端管理数据库中。

公开(公告)号：WO2008019122A2

公开(公告)日：2008-02-14

申请号：PCT/US2007/017460

申请日：2007-08-07

Applicant: INTERNATIONAL RECTIFIER CORPORATION ,  STRYDOM, Johan Tjeerd ,  HONDA, Jun

Inventor： STRYDOM, Johan Tjeerd ,  HONDA, Jun

IPC: H03F3/217

CPC classification number: H03F3/217 ,  H03F1/305

Abstract: A method of minimizing an audible click noise from a speaker in a Class D audio power amplifier upon shutdown or startup of a switching stage having two switches series connected at a node, the speaker being connected to the node via an output filter comprising an inductor and a capacitor, the switches being controlled by a controller. The method including the steps of determining a timing interval at the node to transition a peak voltage of the capacitor, the capacitor voltage being a speaker voltage; and eliminating the audible transient voltage excursion across the speaker that causes a click noise during the timing interval, wherein at startup ON and OFF times of the switches are incrementally increased from zero to a normal mode and at shutdown the ON OFF times of the switches are incrementally decreased from the normal mode to zero.

Abstract translation: 一种用于在关闭或启动具有在节点处连接的两个开关串联的开关级时使来自D类音频功率放大器的扬声器的可听见咔哒噪声最小化的方法，所述扬声器连接到节点 经由包括电感器和电容器的输出滤波器，所述开关由控制器控制。 所述方法包括以下步骤：确定所述节点处的时序间隔以转变所述电容器的峰值电压，所述电容器电压是扬声器电压; 以及消除在定时间隔期间在扬声器两端引起卡嗒声的可听见的瞬态电压偏移，其中在开关的开启和关闭时间从零增加到正常模式并且在关闭时开关的开启关闭时间是 从正常模式递增地减少到零。

公开(公告)号：WO2005121825A2

公开(公告)日：2005-12-22

申请号：PCT/US2005019517

申请日：2005-06-02

Applicant: INT RECTIFIER CORP ,  SCHAFFER CHRISTOPHER P ,  STRYDOM JOHAN ,  CIUFFOLI ANDREA

Inventor： SCHAFFER CHRISTOPHER P ,  STRYDOM JOHAN ,  CIUFFOLI ANDREA

IPC: G01R1/073 ,  G01R31/26

CPC classification number: G01R1/0735

Abstract: A testing apparatus and method for testing a semiconductor device, and more particularly a test arrangement for measuring a guaranteed power loss of a semiconductor module, not requiring the module to have on-board decoupling capacitors for the power loss test. The conventional pogo-pin array and test socket are replaced by a novel low cost anisotropic conductive elastomer and a low cost socket, the conductive polymer providing electrical communication between the socket and the module under test.

Abstract translation: 一种用于测试半导体器件的测试装置和方法，更具体地，用于测量半导体模块的有保证功率损耗的测试装置，不需要该模块具有用于功率损耗测试的板上去耦电容器。 常规的弹簧针阵列和测试插座由新颖的低成本各向异性导电弹性体和低成本插座代替，导电聚合物在插座和被测模块之间提供电气连接。

公开(公告)号：WO2014105887A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/077667

申请日：2013-12-24

Applicant: EFFICIENT POWER CONVERSION CORPORATION ,  REUSCH, David ,  STRYDOM, Johan Tjeerd

Inventor： REUSCH, David ,  STRYDOM, Johan Tjeerd

IPC: H05K1/11

CPC classification number: H01L27/0629 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/15192 ,  H02M7/003 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0265 ,  H05K2201/0792 ,  H05K2201/10166 ,  H01L2924/00

Abstract: A high efficient, single sided printed circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract translation: 高效，单面印刷电路板布局设计，提供磁场自消除和降低的寄生电感，而与板厚无关。 低功率环路延伸穿过电路板顶层上的有源和无源器件，其中通孔将功率回路连接到板的内层中的返回路径。 通过将内层返回路径直接定位在顶层上的功率环路径下方，可以降低功率回路部分功率回路在顶层上的磁效应。

公开(公告)号：WO2005121825B1

公开(公告)日：2006-08-03

申请号：PCT/US2005019517

申请日：2005-06-02

Applicant: INT RECTIFIER CORP ,  SCHAFFER CHRISTOPHER P ,  STRYDOM JOHAN ,  CIUFFOLI ANDREA

Inventor： SCHAFFER CHRISTOPHER P ,  STRYDOM JOHAN ,  CIUFFOLI ANDREA

IPC: G01R31/26 ,  G01R1/073

CPC classification number: G01R1/0735

Abstract: A testing apparatus and method for testing a semiconductor device, and more particularly a test arrangement for measuring a guaranteed power loss of a semiconductor module, not requiring the module to have on-board decoupling capacitors for the power loss test. The conventional pogo-pin array and test socket are replaced by a novel low cost anisotropic conductive elastomer and a low cost socket, the conductive polymer providing electrical communication between the socket and the module under test.

Abstract translation: 一种用于测试半导体器件的测试设备和方法，并且更具体地涉及一种用于测量半导体模块的保证功率损耗的测试装置，其不需要模块具有用于功率损耗测试的板上去耦电容器。 传统的弹簧针阵列和测试插座被新型低成本各向异性导电弹性体和低成本插座取代，导电聚合物提供插座和被测模块之间的电气通信。

公开(公告)号：WO2005121825A3

公开(公告)日：2005-12-22

申请号：PCT/US2005/019517

申请日：2005-06-02

Applicant: INTERNATIONAL RECTIFIER CORPORATION ,  SCHAFFER, Christopher P. ,  STRYDOM, Johan ,  CIUFFOLI, Andrea

Inventor： SCHAFFER, Christopher P. ,  STRYDOM, Johan ,  CIUFFOLI, Andrea

IPC: G01R31/26

Abstract: A testing apparatus and method for testing a semiconductor device, and more particularly a test arrangement for measuring a guaranteed power loss of a semiconductor module, not requiring the module to have on-board decoupling capacitors for the power loss test. The conventional pogo-pin array and test socket are replaced by a novel low cost anisotropic conductive elastomer and a low cost socket, the conductive polymer providing electrical communication between the socket and the module under test.