公开(公告)号：WO2007058854A3

公开(公告)日：2009-05-07

申请号：PCT/US2006043520

申请日：2006-11-10

Applicant: INT RECTIFIER CORP ,  PAVIER MARK ,  SAWLE ANDREW M ,  STANDING MARTIN

Inventor： PAVIER MARK ,  SAWLE ANDREW M ,  STANDING MARTIN

IPC: H01L23/495 ,  H01L23/053 ,  H01L23/12 ,  H01L23/22 ,  H01L23/24 ,  H01L23/28 ,  H01L23/29

CPC classification number: H01L23/043 ,  H01L21/56 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/37 ,  H01L24/83 ,  H01L24/97 ,  H01L25/07 ,  H01L2224/0346 ,  H01L2224/0508 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/40252 ,  H01L2924/403 ,  H01L2924/40407 ,  H01L2224/82

Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

Abstract translation: 一种半导体封装，其包括半导体管芯，管芯周围的绝缘体，以及耦合到管芯的电极的一致的导电焊盘。

公开(公告)号：WO2008106235A9

公开(公告)日：2009-04-23

申请号：PCT/US2008002840

申请日：2008-03-03

Applicant: INT RECTIFIER CORP ,  BODEN MILTON J

Inventor： BODEN MILTON J

IPC: H01L21/335

CPC classification number: H01L29/7813 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766

Abstract: A trench gated MOSFET especially for operation in high radiation environments has a deep auxiliary trench located between the gate trenches. A boron implant is formed in the walls of the deep trench (in an N channel device); a thick oxide is formed in the bottom of the trench, and boron doped polysilicon which is connected to the source electrode fills the trench. The structure has reduced capacitance and improved resistance to single event rupture and single event breakdown and improved resistance to parasitic bipolar action.

Abstract translation: 专门用于在高辐射环境中工作的沟槽门控MOSFET具有位于栅极沟槽之间的深辅助沟道。 在深沟槽的壁中（在N沟道器件中）形成硼注入物; 在沟槽的底部形成厚的氧化物，与源极连接的硼掺杂多晶硅填充沟槽。 该结构具有降低的电容并改善对单事件断裂和单事件击穿的抵抗能力以及改善的寄生双极作用电阻。

公开(公告)号：WO2008021440A4

公开(公告)日：2008-12-31

申请号：PCT/US2007018149

申请日：2007-08-15

Applicant: INT RECTIFIER CORP ,  WU WENKAI ,  SCHUELLEIN GEORGE

Inventor： WU WENKAI ,  SCHUELLEIN GEORGE

IPC: H02H7/10

CPC classification number: H02H7/1213

Abstract: A circuit for detecting faults in at least one converter in a converter system, the at least one converter including a switching stage having high- and low-side switches connected at a switching node and fault circuitry for managing a plurality of fault conditions. The circuit including a gate driver circuit connected to gate terminals of the high- and low-side switches for providing PWM signals to control the switching stage; a comparator circuit for comparing a voltage at the switching node to the input voltage and providing an output signal, the comparator circuit having output, positive and negative terminals; a fourth capacitor connected to the output terminal of the comparator circuit to generate an AC component of the comparator circuit output signal; and a rectifier circuit connected to the fourth capacitor for rectifying the AC component of the comparator circuit and providing a fault-indicating signal to the gate driver. The fault-indicating signal is used to drive the fault circuitry to correct a fault condition selected from the plurality of fault conditions in the converter system.

Abstract translation: 一种用于检测变换器系统中的至少一个变换器中的故障的电路，所述至少一个变换器包括开关级，所述开关级具有在开关节点处连接的高侧和低侧开关以及​​用于管理多个故障状况的故障电路。 该电路包括连接到高侧和低侧开关的栅极端子的栅极驱动器电路，用于提供PWM信号以控制开关级; 比较器电路，用于将开关节点处的电压与输入电压进行比较并提供输出信号，比较器电路具有输出端，正端和负端; 第四电容器，连接到比较器电路的输出端以生成比较器电路输出信号的AC分量; 以及连接到第四电容器的整流器电路，用于整流比较器电路的AC分量并向栅极驱动器提供故障指示信号。 故障指示信号被用于驱动故障电路以校正从变换器系统中的多个故障状况中选择的故障状态。

公开(公告)号：WO2007109301B1

公开(公告)日：2008-10-23

申请号：PCT/US2007006983

申请日：2007-03-20

Applicant: INT RECTIFIER CORP ,  HERMAN THOMAS

Inventor： HERMAN THOMAS

IPC: H01L29/74

CPC classification number: H01L29/7787 ,  H01L27/0605 ,  H01L27/0705 ,  H01L29/2003 ,  H01L29/42316

Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element. The first gate is connected to an input voltage signal such that conduction of the first portion is based on a value of the input voltage signal and the second gate is connected to a predetermined constant voltage such that the second portion of the transistor conducts until a voltage difference between the predetermined constant voltage and a voltage at the source electrode reaches a predetermined level.

Abstract translation: 根据本发明实施例的合并栅极晶体管包括：半导体元件;电连接到半导体元件的顶表面的供电电极;漏电极，电连接到半导体元件的顶表面，并且与半导体元件的顶表面横向间隔开 位于所述供应电极和所述漏极之间并电容耦合到所述半导体元件以形成所述晶体管的第一部分的第一栅极以及与所述第一栅极相邻且位于所述供应电极和所述漏极电极之间的第二栅极 以形成晶体管的第二部分，其中第二栅极也电容耦合到半导体元件。 第一栅极连接到输入电压信号，使得第一部分的导通基于输入电压信号的值，并且第二栅极连接到预定的恒定电压，使得晶体管的第二部分导通直到电压 预定的恒定电压与源电极处的电压之差达到预定水平。

公开(公告)号：WO2008008486A3

公开(公告)日：2008-10-02

申请号：PCT/US2007015980

申请日：2007-07-13

Applicant: INT RECTIFIER CORP ,  HO EDDY YING YIN

Inventor： HO EDDY YING YIN

IPC: H02P21/00 ,  H02P23/00 ,  H02P25/00 ,  H02P27/00

CPC classification number: H02P6/185

Abstract: An apparatus and method for estimating rotor angle information for the control of permanent magnet AC motors having sinusoidal current excitation. The disclosed motor drive can provide full load operation at very low speeds including zero speed without the use of a shaft position sensing device. The rotor angle is estimated through injection of high frequency current, and rotor angle is extracted by a signal-conditioning algorithm, which utilizes current amplitude differential to discriminate the rotor angle. Rotor angle magnetic axis orientation (North or South pole) at startup is detected by comparing time average current ripple (at signal injection frequency) content between two different levels of d-axis current injection.

Abstract translation: 用于估计用于控制具有正弦电流激励的永磁体AC电动机的转子角度信息的装置和方法。 所公开的电机驱动器可以以非常低的速度提供满载运行，包括零速度，而不使用轴位置检测装置。 通过注入高频电流来估算转子角度，通过信号调节算法提取转子角，利用电流幅度差分来确定转子角度。 通过比较两个不同水平的d轴电流注入之间的时间平均电流纹波（信号注入频率）的含量来检测启动时的转子角轴方向（北极或南极）。

公开(公告)号：WO2007089639A3

公开(公告)日：2008-09-25

申请号：PCT/US2007002260

申请日：2007-01-26

Applicant: INT RECTIFIER CORP ,  LEE DONG YOUNG

Inventor： LEE DONG YOUNG

IPC: H03K3/00

CPC classification number: H02M3/07 ,  H02M1/08 ,  H03K17/6871

Abstract: A circuit for using a high voltage gate driver IC (HVIC) for regulation of external floating voltage sources without use of regulation circuits. The circuit including high and low switches; at least one external voltage source coupled to the high and low switches; an HVIC having at least one internal charge pumping voltage source circuit, the HVIC being coupled to gate terminals of the high and low switches; and at least one charge pumping capacitor coupled to the at least one internal charge pumping voltage source circuit for regulating the external voltage of at least one external voltage source.

Abstract translation: 一种用于在不使用调节电路的情况下使用高压栅极驱动器IC（HVIC）来调节外部浮动电压源的电路。 该电路包括高低开关; 耦合到所述高和低开关的至少一个外部电压源; HVIC具有至少一个内部电荷泵浦电压源电路，所述HVIC耦合到所述高和低开关的栅极端子; 以及耦合到所述至少一个内部电荷泵浦电压源电路的至少一个电荷泵浦电容器，用于调节至少一个外部电压源的外部电压。

公开(公告)号：WO2007120769B1

公开(公告)日：2008-09-12

申请号：PCT/US2007009037

申请日：2007-04-13

Applicant: INT RECTIFIER CORP ,  HAUENSTEIN HENNING M

Inventor： HAUENSTEIN HENNING M

IPC: H01L23/02

CPC classification number: H01L25/072 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/73153 ,  H01L2224/732 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/30107 ,  H01L2224/83 ,  H01L2924/00

Abstract: A power semiconductor package that includes at least two semiconductor devices electrically coupled to one another through a common metallic web.

Abstract translation: 一种功率半导体封装，其包括通过公共金属网而彼此电耦合的至少两个半导体器件。

公开(公告)号：WO2006076298A3

公开(公告)日：2008-08-28

申请号：PCT/US2006000704

申请日：2006-01-10

Applicant: INT RECTIFIER CORP ,  CHIOLA DAVIDE

Inventor： CHIOLA DAVIDE

IPC: H01L21/28 ,  H01L21/329 ,  H01L21/44 ,  H01L27/08 ,  H01L29/40 ,  H01L29/47 ,  H01L29/872

CPC classification number: H01L29/8725 ,  H01L27/0814 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/872 ,  Y10S438/963

Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

Abstract translation: 在沟槽内具有差异氧化物厚度的沟槽肖特基二极管的制造方法包括在衬底表面上形成第一氮化物层，并且随后在衬底中形成包括可能的端接沟槽的多个沟槽。 在牺牲氧化层形成和去除之后，沟槽的侧壁和底表面被氧化。 然后将第二氮化物层施加到衬底并被蚀刻，使得第二氮化物层覆盖沟槽侧壁上的氧化物层，但是暴露出沟槽底表面上的氧化物层。 然后，沟槽底表面被再次氧化，然后从侧壁去除剩余的第二氮化物层，导致在每个沟槽的侧壁和底表面上形成不同厚度的氧化物层。 然后用P型多晶硅，去除第一氮化物层和施加到衬底表面上的肖特基势垒金属填充沟槽。

公开(公告)号：WO2007081932A3

公开(公告)日：2008-08-07

申请号：PCT/US2007000490

申请日：2007-01-09

Applicant: INT RECTIFIER CORP ,  BEACH ROBERT ,  BRIDGER PAUL

Inventor： BEACH ROBERT ,  BRIDGER PAUL

IPC: H01L31/00

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7787 ,  H01L29/7789

Abstract: A III-nitride heterojunction semiconductor device that includes a power electrode that is electrically connected to a conductive substrate through a trench in the heterojunction thereof.

Abstract translation: III族氮化物异质结半导体器件，其包括通过其异质结中的沟槽电连接到导电衬底的功率电极。

公开(公告)号：WO2007089910A3

公开(公告)日：2008-07-31

申请号：PCT/US2007002797

申请日：2007-01-30

Applicant: INT RECTIFIER CORP ,  LEE DONG YOUNG

Inventor： LEE DONG YOUNG

IPC: G09G3/28

CPC classification number: G09G3/2965 ,  G09G2330/12

Abstract: A PDP sustain driver circuit including at least one high voltage gate driver IC (HVIC) having internal logic functions. The PDP sustain driver circuit including a plurality of switches, the HVIC providing a unique control signal to at least one first and at least one second switch. The internal logic functions including a sensing circuit for sensing information about the at least one second switch; and a reporting circuit for reporting or displaying a signal indicating at least one of a plurality of failure modes of the at least one second switch.

Abstract translation: 一种PDP维持驱动器电路，包括至少一个具有内部逻辑功能的高压栅极驱动器IC（HVIC）。 包括多个开关的PDP维持驱动器电路，HVIC向至少一个第一和至少一个第二开关提供唯一的控制信号。 内部逻辑功能包括用于感测关于至少一个第二开关的信息的感测电路; 以及报告电路，用于报告或显示指示所述至少一个第二开关的多个故障模式中的至少一个的信号。