公开(公告)号：WO2019066937A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054487

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： DOMINGUEZ, Juan E. ,  KIM, Hyoung Il ,  KHALAF, Bilal ,  MEYERS, John Gary

IPC分类号： H01L25/065 ,  H01L23/12 ,  H01L23/00

摘要： A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.

公开(公告)号：WO2017048428A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/046952

申请日：2016-08-14

申请人： INTEL CORPORATION

发明人： PON, Florence, R. ,  KHALAF, Bilal ,  SHOJAIE, Saeed, S.

IPC分类号： H01L23/00 ,  H01L21/66 ,  G01R31/28 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/573 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L25/0652 ,  H01L2223/54453 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.

摘要翻译： 可以用在微电子封装的一侧或底部形成的调试访问端口来制造微电子封装。 在一个实施例中，调试访问端口可以形成在靠近微电子封装侧的封装材料内。 在另一个实施例中，调试访问端口可以形成在靠近微电子封装侧的微电子封装的微电子插入器中。 在另一实施例中，调试访问端口可以形成在微电子封装底部并且可以包括焊接触点。

公开(公告)号：WO2017188938A1

公开(公告)日：2017-11-02

申请号：PCT/US2016/029394

申请日：2016-04-26

申请人： INTEL CORPORATION

发明人： KHALAF, Bilal

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/49

摘要： A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.

摘要翻译： 可以制造微电子封装，其具有连接到微电子衬底的微电子管芯堆叠和与微电子管芯堆叠分离的至少一个微电子器件，该微电子器件在一个 微电子管芯堆内的微电子管芯。 在一个实施例中，微电子管芯堆叠可以具有多个堆叠的微电子管芯，其中多个微电子管芯中的一个微电子管芯具有比多个微电子管芯中的另一个微电子管芯更大的覆盖区，并且其中至少一个微电子 器件连接到具有更大占用面积的多个微电子管芯中的一个微电子管芯。

公开(公告)号：WO2017019153A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/032901

申请日：2016-05-17

申请人： INTEL CORPORATION

发明人： KHALAF, Bilal

IPC分类号： G06F13/16 ,  G06F13/12 ,  G06F15/78 ,  G06F12/02

CPC分类号： H01L25/18 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  H01L23/538 ,  H01L25/50 ,  H01L2224/16225

摘要： Techniques and mechanisms for a SIP to control access to a non-volatile memory of another packaged device. In an embodiment, the SIP includes interface a processor, a local memory and a memory controller that provides the processor with access to the local memory. The SIP further includes interface hardware to couple the SIP to the packaged device, wherein the processor of the SIP accesses a non-volatile memory of the packaged device via the memory controller of the SIP. In another embodiment, the interface hardware of the SIP includes a first plurality of contacts to couple to the packaged device, as well as a second plurality of contacts. An interface standard describe an arrangement of interface contacts, wherein, of a first arrangement of the first contacts and the second arrangement of the second contacts, only the second arrangement conforms to the described arrangement of interface contacts.

摘要翻译： 用于SIP控制对另一封装设备的非易失性存储器的访问的技术和机制。 在一个实施例中，SIP包括处理器，本地存储器和为处理器提供对本地存储器的访问的存储器控​​制器的接口。 SIP还包括将SIP耦合到打包设备的接口硬件，其中SIP的处理器经由SIP的存储器控​​制器访问打包设备的非易失性存储器。 在另一实施例中，SIP的接口硬件包括耦合到封装装置的第一多个触点以及第二多个触点。 接口标准描述了接口触点的布置，其中，第一触点的第一布置和第二触点的第二布置中，只有第二布置符合所描述的界面触点布置。

公开(公告)号：WO2018111253A1

公开(公告)日：2018-06-21

申请号：PCT/US2016/066523

申请日：2016-12-14

申请人： INTEL CORPORATION

发明人： XU, Yi Elyn ,  KHALAF, Bilal

IPC分类号： H01L23/522 ,  H01L23/28 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

摘要： An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.

公开(公告)号：WO2017052767A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/044520

申请日：2016-07-28

申请人： INTEL CORPORATION

发明人： MEYERS, John G. ,  KHALAF, Bilal ,  GOGINENI, Sireesha ,  LONG, Brian J.

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/585 ,  H01L21/52 ,  H01L22/32 ,  H01L22/34 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15162 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15333 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

摘要翻译： 便于与封装器件的一个或多个集成电路（IC）管芯连接的技术和机制。 在一个实施例中，封装器件包括耦合到封装的第一侧的第一衬底和耦合到封装件与第一侧相对的第二侧的第二衬底。 通过第一基板耦合到设置在封装中的一个或多个IC芯片的电路包括设置在第一基板的悬臂部分处的电路结构。 悬臂部分延伸穿过第一侧的边缘和第二侧的边缘中的一个或两个。 在另一个实施例中，设置在第二基板上的硬件接口使得能够将封装的装置耦合到另一装置。

公开(公告)号：WO2018063188A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054144

申请日：2016-09-28

申请人： INTEL CORPORATION ,  SHOJAIE, Saeed ,  KIM, Hyoung IL Andrew ,  KHALAF, Bilal ,  LAI, Min-Tih Ted

发明人： SHOJAIE, Saeed ,  KIM, Hyoung IL Andrew ,  KHALAF, Bilal ,  LAI, Min-Tih Ted

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/495

摘要： A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.

摘要翻译： 包括在芯片边缘处在电介质脊上方偏转的引线键合的键合线系统。 偏转的引线键合允许降低Z形轮廓和减小X-Y足迹。 该键合线系统可以包括堆叠裸片配置，其中堆叠裸片被引线键合并且堆叠裸片键合引线在堆叠裸片边缘处的电介质脊上方偏转。

公开(公告)号：WO2018004695A1

公开(公告)日：2018-01-04

申请号：PCT/US2016/040868

申请日：2016-07-01

申请人： INTEL CORPORATION

发明人： KHALAF, Bilal ,  GUO, Mao

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L25/065

摘要： Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

摘要翻译： 披露了电子器件封装技术。 在一个实例中，电子器件包括具有键合指的衬底，耦合到衬底并具有键合焊盘的管芯，耦合在键合焊盘和键合指之间的第一键合线，以及耦合在键合 垫和键指。 第一键合线在键合焊盘上的焊盘焊球与键合手指上的手指焊球之间反向键合。 第二键合线正向键合在垫焊料上的辅助焊盘焊球和邻近手指焊球的键合手指之间。 还公开了相关的系统和方法。

公开(公告)号：WO2017172061A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/017238

申请日：2017-02-09

申请人： INTEL CORPORATION

发明人： PON, Florence R. ,  KHALAF, Bilal ,  SHOJAIE, Saeed S.

IPC分类号： H01L25/18 ,  H01L25/16 ,  H01L25/11 ,  H01L25/07 ,  H01L25/00 ,  H01L21/56

CPC分类号： H05K3/284 ,  G01R31/2818 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.

摘要翻译： 实施例通常针对埋入式电气调试接入端口。 装置的实施例包括衬底或印刷电路板; 与衬底或印刷电路板耦合的一个或多个电子组件; 与衬底或印刷电路板耦合的一个或多个电接入端口，每个电接入端口包括导电材料; 以及封装材料，所述封装材料封装所述一个或多个存取端口，其中所述一个或多个存取端口电连接到所述设备的一个或多个电路以提供对所述设备的调试访问。