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    식별키 생성 장치 및 방법
    2.
    发明申请
    식별키 생성 장치 및 방법 审中-公开
    用于产生识别钥匙的装置和方法

    公开(公告)号：WO2015053441A1

    公开(公告)日：2015-04-16

    申请号：PCT/KR2014/001251

    申请日：2014-02-17

    Applicant: (주) 아이씨티케이

    Inventor： 최병덕 ,  김동규

    IPC: G06F21/73

    CPC classification number: H01L23/573 ,  G06F17/5072 ,  G06F21/73 ,  G09C1/00 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0629 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

    Abstract: 전도성 레이어의 제조 공정 상의 공정 편차를 이용하여 식별키를 생성하는 장치가 제공된다. 상기 식별키 생성 장치는, 반도체 칩에 포함되는 제1 전도성 레이어와 연결되는 제1 컨택 - 제1 노드는 상기 제1 전도성 레이어와 상기 제1 컨택이 전기적으로 연결되어 형성됨 -; 상기 반도체 칩에 포함되는 제2 전도성 레이어와 연결되는 제2 컨택 - 제2 노드는 상기 제2 전도성 레이어와 상기 제2 컨택이 전기적으로 연결되어 형성되고, 상기 제1 컨택과 상기 제2 컨택은 상기 반도체 칩의 패터닝 레이아웃 상에서 상기 제1 노드와 상기 제2 노드가 단락되지 않는 것을 보장하는 최소 스패이싱 값 미만의 스패이싱 값을 가짐 --및 상기 제1 노드와 상기 제2 노드 사이가 전기적으로 단락되는지의 여부를 식별하여 식별키를 생성하는 독출부를 포함할 수 있다.

    Abstract translation: 提供了一种通过使用导电层制造工艺中的工艺变化来产生识别键的装置。 用于产生识别键的装置包括：第一触点，其连接到包括在半导体芯片中的第一导电层，其中第一节点由第一导电层和第一触点之间的电连接形成; 第二触点，其连接到包括在所述半导体芯片中的第二导电层，其中通过所述第二导电层和所述第二触点之间的电连接形成第二节点，并且其中所述第一触点和所述第二触点具有间隔 值小于最小间隔值，其确保第一节点和第二节点在半导体芯片上的图案化布局上不短路; 以及用于识别第一节点和第二节点是否电短路的读取单元，以及用于提供识别密钥。

    VERIFICATION OF PERFORMANCE ATTRIBUTES OF PACKAGED INTEGRATED CIRCUITS
    4.
    发明申请
    VERIFICATION OF PERFORMANCE ATTRIBUTES OF PACKAGED INTEGRATED CIRCUITS 审中-公开
    包装集成电路性能特性的验证

    公开(公告)号：WO2007080375A1

    公开(公告)日：2007-07-19

    申请号：PCT/GB2007/000015

    申请日：2007-01-03

    Applicant: INGENIA HOLDINGS (UK) LIMITED ,  COWBURN, Russell, Paul ,  BUCHANAN, James, David, Ralph

    Inventor： COWBURN, Russell, Paul ,  BUCHANAN, James, David, Ralph

    IPC: H01L23/544

    CPC classification number: G01R31/31719 ,  G01R31/2896 ,  G01R31/31718 ,  H01L23/544 ,  H01L23/573 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Packaged integrated circuits (ICs) of some types, such as processors, are graded and sold according to a performance scale, such as maximum specified clock speed, set by the manufacturer as a result of testing. As a record of this grading some part of the package, usually the upper surface, is marked with the specified performance attribute. However, criminal activity has developed where the packaging is relabelled to show a higher specification so the ICs can be fraudulently resold at a higher price. To address this problem, the invention envisages that manufacturers maintaining a product database for each packaged IC which logs not only the performance specification, but also a digital signature derived from a speckle pattern obtained from the packaging. Subsequently, any packaged IC can be rescanned to interrogate its speckle pattern and recompute the signature. The signature is then used to find the product in the database, whereby the originally specified performance attribute is retrieved. The fraud is then detectable. This method can be used to test products returned under a warranty claim, for example.

    Abstract translation: 某些类型的封装集成电路（如处理器）根据测试结果由制造商设定的性能规模进行分级和出售，例如最大规定的时钟速度。 作为此分级的记录，包的某些部分（通常为上表面）标有指定的性能属性。 然而，犯罪活动已经发展到包装被重新标榜以显示更高的规格，所以IC可以以更高的价格欺诈地转售。 为了解决这个问题，本发明设想制造商为每个封装的IC维护产品数据库，其不仅记录性能规范，而且还记录从包装获得的散斑图案中得到的数字签名。 随后，可以重新扫描任何封装的IC以询问其斑点图案并重新计算签名。 然后使用签名在数据库中查找产品，从而检索最初指定的性能属性。 然后可以检测到欺诈。 例如，该方法可用于测试以保修索赔退回的产品。

    SCREENING DEVICE FOR INTEGRATED CIRCUITS
    5.
    发明申请
    SCREENING DEVICE FOR INTEGRATED CIRCUITS 审中-公开
    屏蔽集成电路

    公开(公告)号：WO02063687A2

    公开(公告)日：2002-08-15

    申请号：PCT/DE0200470

    申请日：2002-02-08

    Applicant: INFINEON TECHNOLOGIES AG ,  AUMUELLER CHRISTIAN ,  JANKE MARCUS ,  HOFREITER PETER

    Inventor： AUMUELLER CHRISTIAN ,  JANKE MARCUS ,  HOFREITER PETER

    IPC: H01L23/58 ,  H01L23/66

    CPC classification number: H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a screening device comprising means for optical and/or electrical screening which are arranged in the semiconductor chip on the side of the integrated circuit facing the substrate. Preferred embodiments use an SOI substrate with the integrated circuit in the body silicon layer (3) and with the isolator layer (2) as an optical screening device of the bulk silicon layer (1). Electrical conductors (5) can be provided in the bulk silicon layer as an optical and electrical screening device and can be connected to the circuit by means of platings (4).

    Abstract translation: 筛选装置包括用于光学和/或电屏蔽装置，该装置是在面向设置在半导体芯片的集成电路的基板的一侧上。 优选实施例使用在体内具有硅层（3）在所述集成电路和所述绝缘层（2）如（1）前体硅层的光学筛选SOI衬底。 在所述体硅层的电导体（5）的光学和电屏蔽设置有通孔（4）可连接到所述电路。

    METHOD AND APPARATUS USING SILICIDE LAYER FOR PROTECTING INTEGRATED CIRCUITS FROM REVERSE ENGINEERING
    7.
    发明申请
    METHOD AND APPARATUS USING SILICIDE LAYER FOR PROTECTING INTEGRATED CIRCUITS FROM REVERSE ENGINEERING 审中-公开
    使用硅化物层保护逆向工程集成电路的方法与装置

    公开(公告)号：WO00065654A1

    公开(公告)日：2000-11-02

    申请号：PCT/US2000/010106

    申请日：2000-04-14

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092

    CPC classification number: H01L23/573 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823835 ,  H01L27/02 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting the at least one active area with another area through the silicide area formed on the selected substrate area. In a preferred embodiment a silicide layer formed on a first active area is interconnectingly merged laterally with a silicide layer formed on a second active area through the silicide layer formed on the selected substrate area.

    Abstract translation: 一种用于保护半导体集成电路免受逆向工程的方法和装置。 半导体有源区形成在基板上。 在半导体有源区域的至少一个有效区域上方以及选定的衬底区域上形成硅化物层，用于通过形成在所选择的衬底区域上的硅化物区域将至少一个有源区域与另一区域互连。 在优选实施例中，形成在第一有源区上的硅化物层与通过形成在所选择的衬底区域上的硅化物层形成在第二有源区上的硅化物层横向地相互合并。

    SEMICONDUCTOR CHIP AND WAFER WITH A PROTECTIVE LAYER, ESPECIALLY MADE OF CERAMIC
    8.
    发明申请
    SEMICONDUCTOR CHIP AND WAFER WITH A PROTECTIVE LAYER, ESPECIALLY MADE OF CERAMIC 审中-公开
    半导体芯片和外延片与保护涂层，特别是陶瓷

    公开(公告)号：WO1998024121A1

    公开(公告)日：1998-06-04

    申请号：PCT/DE1997002562

    申请日：1997-11-05

    Applicant: SIEMENS AKTIENGESELLSCHAFT ,  NEU, Achim ,  STAMPKA, Peter

    Inventor： SIEMENS AKTIENGESELLSCHAFT

    IPC: H01L21/56

    CPC classification number: H01L23/573 ,  H01L23/291 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention pertains to semiconductor chips and wafers presenting on at least one face a protective layer applied according to a flame or plasma projection method. The protective layer is mainly ceramic. Between the protective layer and the chip or wafer surface, there can be an intermediate layer made of a non-electroconductive and moisture-proof material. The intermediate layer has an adhesive function and improves the chip or wafer surface protection against chemical and mechanical degradations and makes the unauthorized detection of circuit systems difficult.

    Abstract translation: 本发明涉及半导体芯片和晶片具有在至少一个表面上的火焰或等离子体喷涂法保护层施加的涂层。 所述保护层优选由陶瓷制成。 在保护层和芯片或晶片表面之间，中间层可以由非导电和防潮材料制成。 中间层用作接合层，提高了芯片或晶片表面的保护。 该保护层保护芯片或晶片表面抗化学和机械损伤和使得难以半导体芯片的电路不公平的检测。

    SECURE SEMICONDUCTOR DEVICE
    9.
    发明申请
    SECURE SEMICONDUCTOR DEVICE 审中-公开
    安全半导体器件

    公开(公告)号：WO1997022990A1

    公开(公告)日：1997-06-26

    申请号：PCT/US1996019808

    申请日：1996-12-12

    Applicant: INTEL CORPORATION ,  ROLLENDER, Matthew ,  HIRT, Ray

    Inventor： INTEL CORPORATION

    IPC: H01L21/02

    CPC classification number: H01L27/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/24 ,  H01L23/573 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48137 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/3025 ,  H01L2924/00

    Abstract: A method for securing confidential circuitry from observation by unauthorized inspection, and a secure circuit immune from unauthorized inspection according to the method. In one embodiment, confidential data or circuitry is placed on a face of separate silicon layers (42, 44), each silicon layer having part of a circuit. Neither silicon layer is intelligible without the other, yet neither can be observed without destroying the other. The two silicon layers are juxtaposed, the face of the first silicon layer (42) flush against and fused to the face of the second silicon layer (44), the confidential circuits on each silicon layer connecting directly with circuits on the other silicon layer without external connectors. Data stored on each face is erased or destroyed when the silicon layers are separated or one of the silicon layers is destroyed. Violence to either silicon layer, or exposure of either silicon layer to light, destroys the data or circuitry on at least one silicon layer of silicon, making the data or circuitry unreadable.

    Abstract translation: 一种用于通过未经授权的检查来保护机密电路免于观察的方法，以及根据该方法免于未经授权的检查的安全电路。 在一个实施例中，机密数据或电路放置在单独硅层（42,44）的表面上，每个硅层具有电路的一部分。 没有一个硅层是不可理解的，但是两者都不能在没有破坏另一个的情况下被观察到。 两个硅层并置，第一硅层（42）的表面与第二硅层（44）的表面齐平并熔合，每个硅层上的保密电路直接与另一个硅层上的电路连接，而没有 外部连接器 当硅层分离或硅层中的一个被破坏时，存储在每个面上的数据被擦除或破坏。 暴露于硅层或将硅层暴露于光，会破坏至少一个硅层的硅层上的数据或电路，从而使数据或电路无法读取。

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