Abstract:
An integrated circuit package (210) comprising a substrate that has a dielectric layer and a micro-filled via formed substantially in the center of a hole in the dielectric layer is disclosed. The IC package substrate has at least one chip bonding pad and one ball attach pad (201) that are electrically coupled to each other by the micro-filled via. The micro-filled via is formed of a material called a "micro-filled via material" that includes a binding material and optionally includes a number of particles dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal.
Abstract:
A micro filled material (801) includes a binding material (802) and optionally includes a number of particles (803). The binding material (802) and the particles (803) can be formed of any conductive or nonconductive material. Using such a micro filled via material (801), an electrical conductor is formed in a substrate (825) for supporting one or more electronic components using the following steps: placing the micro filled via material (801) between two conductive layers (810, 820) at various locations in a substrate (825) at which an electrical conductor is to be formed; and optionally programming the micro filled via material (801) to reduce the resistance of, or to form an electrical conductor.