公开(公告)号：WO1996030938A2

公开(公告)日：1996-10-03

申请号：PCT/US1996003367

申请日：1996-03-12

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  ITO, Takeshi ,  SCOTT, Michael, C. ,  MCMILLAN, Larry, D.

IPC: H01L21/3205

CPC classification number: C23C18/1216 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  C23C16/4412 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/1279 ,  C23C18/1283 ,  C23C18/1295 ,  C23C26/02 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01C7/1013 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/10805 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/257 ,  H01L41/318 ,  H05K3/105

Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

Abstract translation: 将含有金属的液体前体施加到基底上，进行RTP烘烤并退火以形成层状超晶格材料。 设计特殊的聚氧化烷基化前体溶液通过添加包括化学计量过量的铋和钽的掺杂剂来优化相应的金属氧化物材料的极化率。 RTP烘焙过程对于优化所得金属氧化物的极化率是特别有利的。

公开(公告)号：WO1996013860A1

公开(公告)日：1996-05-09

申请号：PCT/US1995013379

申请日：1995-10-26

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  WATANABE, Hitoshi ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  McMILLAN, Larry, D.

IPC: H01L27/115

CPC classification number: H01L27/11502 ,  G11C11/22

Abstract: A non-volatile integrated circuit memory (10, 11, 100, 200) in which the memory cell (10, 11) includes a first transistor gate (19, 36) overlying a first channel region (44A), a ferroelectric material (48) overlying a second channel region (44B), and a second transistor gate (23, 37) overlying a third channel region (44C). The channel regions (44A, 44B, 44C) are connected in series, and preferably are contiguous portions of a single semiconducting channel (44). The first channel (44A) is connected to a plate voltage that is 20 % to 50 % of the coercive voltage of the ferroelectric material. A sense amplifier (110) is connected to the third channel region (44C) via a bit line (108). The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.

Abstract translation: 一种非易失性集成电路存储器（10,11,100,200），其中存储单元（10,11）包括覆盖第一沟道区（44A）的第一晶体管栅极（19,36），铁电材料（48） ）覆盖第二沟道区（44B），以及覆盖第三沟道区（44C）的第二晶体管栅极（23,37）。 沟道区域（44A，44B，44C）串联连接，优选地是单个半导体沟道（44）的邻接部分。 第一通道（44A）与铁电体的矫顽电压的20％〜50％的板电压连接。 读出放大器（110）经由位线（108）连接到第三通道区域（44C）。 在读出逻辑“1”状态之后，位线的上升通过在读出放大器上升之前关闭第三通道来防止铁电材料的干扰。

公开(公告)号：WO1994010702A1

公开(公告)日：1994-05-11

申请号：PCT/US1993010021

申请日：1993-10-21

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  YOSHIMORI, Hiroyuki ,  WATANABE, Hitoshi ,  PAZ DE ARAUJO, Carlos, A. ,  McMILLAN, Larry, D. ,  CUCHIARO, Joseph, D. ,  SCOTT, Michael, C.

IPC: H01L21/316

CPC classification number: H01L27/11502 ,  C23C16/45561 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A liquid precursor containing a metal is applied to a substrate (18), RTP baked, and annealed to form a layered superlattice material (30). To obtain good electrical properties, prebaking the substrate (18) in oxygen in the RTP and anneal are essential, except for high bismuth content precursors. Excess bismuth between 110 % and 140 % of stoichiometry and RTP temperature of 750 DEG C is optimum. The film is formed in two layers (30A, 30B), the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor.

Abstract translation: 将含有金属的液体前体施加到基材（18）上，进行RTP烘焙并退火以形成层状超晶格材料（30）。 为了获得良好的电学性能，将基材（18）在RTP中进行氧预处理和退火是重要的，除了高铋含量前体。 化学计量的110％至140％之间的过量铋和750℃的RTP温度是最佳的。 膜形成为两层（30A，30B），其中第一层使用化学计量的前体，其中第二层使用过量的铋前体。

公开(公告)号：WO1996029712A1

公开(公告)日：1996-09-26

申请号：PCT/US1996003519

申请日：1996-03-14

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  ITO, Takeshi ,  HIRAIDE, Shuzo ,  SCOTT, Michael, C. ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

IPC: H01C07/10

CPC classification number: C23C18/1216 ,  C23C16/45561 ,  C23C18/1225 ,  C23C18/1295 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01C7/1013 ,  H01C7/112 ,  H01C17/075 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55

Abstract: A thin-film zinc oxide varistor (10) for use in integrated circuits and the like is produced by applying a polyoxyalkylated metal complex, such as a metal alkoxycarboxylate, to a substrate (12, 14, and 16) for the formation of a dried non-ohmic layer (18). The method of production includes the steps of providing a substrate and a precursor solution including a polyoxyalkylated zinc complex (P22, P24), coating a portion of the substrate with the precursor solution (P26), drying the coated substrate (P32), and crystallizing the dried thin-film zinc oxide layer (P30). The resultant crystalline zinc oxide varistor layer (18) may be doped with bismuth, yttrium, praseodymium, cobalt, antimony, manganese, silicon, chromium, titanium, potassium, dysprosium, cesium, cerium, and iron to provide a non-ohmic varistor. The varistor layer (10) is annealed at a temperature ranging from about 400 to about 1000 DEG C to provide a layer having a thickness ranging from about 50 nanometers to about 500 nanometers and an average grain size diameter less than about 200 nanometers.

Abstract translation: 用于集成电路等的薄膜氧化锌变阻器（10）通过将诸如金属烷氧基羧酸盐的聚氧化烷基化金属络合物施加到基底（12,14和16）上来制备，以形成干燥 非欧姆层（18）。 制造方法包括以下步骤：提供包含聚氧化烷基化锌络合物（P22，P24）的基材和前体溶液，用前体溶液（P26）涂布基材的一部分，干燥涂布的基材（P32），使结晶 干燥的薄膜氧化锌层（P30）。 所得结晶氧化锌变阻器层（18）可掺杂铋，钇，镨，钴，锑，锰，硅，铬，钛，​​钾，镝，铯，铈和铁，以提供非欧姆变阻器。 压敏电阻层（10）在约400至约1000℃的温度下退火，以提供厚度范围为约50纳米至约500纳米，平均粒径直径小于约200纳米的层。

公开(公告)号：WO1996029727A1

公开(公告)日：1996-09-26

申请号：PCT/US1996003522

申请日：1996-03-14

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  ITO, Takeshi ,  PAZ DE ARAUJO, Carlos, A. ,  WATANABE, Hitoshi ,  SCOTT, Michael, C.

IPC: H01L21/3205

CPC classification number: C23C18/1295 ,  C23C16/45561 ,  C23C18/1216 ,  C23C18/1225 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01C7/1013 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/10805 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A liquid precursor containing a metal is applied to a first electrode, RTP backed at a temperature of 700 DEG C, and annealed at the same temperature from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700 DEG C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8

Abstract translation: 将含有金属的液体前体施加到第一电极，RTP在700℃的温度下反应，并在相同温度下退火3至5小时以形成层状超晶格材料。 形成第二电极以形成电容器，并且在700℃的温度下进行第二次退火。如果该材料是钽酸铋锶，则该前体包含铀的锶摩尔当量，铋的摩尔当量铋和 w摩尔当量的钽，其中0.8≤0.02，2.0≤v≤2.3和1.9≤w≤2.1。

公开(公告)号：WO1995026570A1

公开(公告)日：1995-10-05

申请号：PCT/JP1995000533

申请日：1995-03-23

Applicant: OLYMPUS OPTICAL CO., LTD. ,  SYMETRIX CORPORATION ,  NAKANO, Hiroshi ,  OHMURA, Masayoshi

Inventor： OLYMPUS OPTICAL CO., LTD. ,  SYMETRIX CORPORATION

IPC: H01L27/10

CPC classification number: H01L27/11502 ,  G11C11/22 ,  G11C11/5657

Abstract: A ferroelectrique capacitor used in a memory cell section of a ferroelectric memory device comprises a polarization P1 region having a film thickness (d) and an area S1, and a polarization P2 region which is a component in the P1 direction of oblique polarization P2 having only one electrode section and an area S2. The combined hysteresis characteristics of the polarizations P1 and P2 include a twisted hysteresis characteristic. When the memory state of the twisted hysteresis characteristic is "0" and "1", nondestructive readout is possible due to a back switching phenomenon. A ferroelectric memory device of another mode of this invention comprises a ferroelectric capacitor (11) which has a multiplex hysteresis characteristic having at least three stable polarization values attributed to the twisted hysteresis characteristic and is formed by sandwiching a ferroelectric material which stores multilevel voltages resulting from the multiplex hysteresis characteristic as information between electrode materials, dielectric capacitor (12) connected in series to the capacitor (11), and voltage-current converting element (16) which reads out the multilevel information stored in the capacitor (11).

Abstract translation: 在铁电存储器件的存储单元部分中使用的铁电电容器包括具有膜厚度（d）和面积S1的极化P1区域和仅具有倾斜极化点P2的P1方向上的分量的极化P2区域 一个电极部分和一个区域S2。 极化P1和P2的组合滞后特性包括扭曲滞后特性。 当扭转滞后特性的存储状态为“0”和“1”时，由于反向切换现象，可以进行非破坏性读出。 本发明另一种模式的铁电存储器件包括具有归结于扭曲滞后特性的至少三个稳定极化值的复用滞后特性的铁电电容器（11），并且通过夹持铁电材料形成，所述铁电材料存储多 作为与电容器（11）串联连接的电极材料，介质电容器（12）之间的信息的多路复用滞后特性，以及读出存储在电容器（11）中的多电平信息的电压 - 电流转换元件（16）。

公开(公告)号：WO1994010704A1

公开(公告)日：1994-05-11

申请号：PCT/US1993010127

申请日：1993-10-21

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  YOSHIMORI, Hiroyuki ,  WATANABE, Hitoshi ,  PAZ DE ARUAJO, Carlos, A. ,  HIRAIDE, Shuzo ,  McMILLAN, Larry, D. ,  MIHARA, Takashi

IPC: H01L27/115

CPC classification number: H01L27/11502 ,  C23C16/45561 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A method of fabricating a layered superlattice DRAM (100) compatible with conventional silicon CMOS technology. A MOSFET (72) is formed on a silicon substrate (71). A thick layer (77D) of BPSG followed by a thin SOG layer (77E) overlies the MOSFET (72). A capacitor (80) is formed by depositing a layer (81) of platinum, annealing, depositing an intermediate layer (84) comprising a layered superlattice material, annealing, depositing a second layer (84) of platinum, then patterning the capacitor (80). Another SOG layer (86) is deposited, contact holes (106, 107) to the MOSFET (72) and capacitor (80) are partially opened, the SOG (86) is annealed, the contact holes (106, 107) are completely opened, and a Pt/Ti/PtSi wiring layer (88, 288) is deposited.

Abstract translation: 一种制造与常规硅CMOS技术兼容的分层超晶格DRAM（100）的方法。 在硅衬底（71）上形成MOSFET（72）。 BPSG的厚层（77D）之后是薄的SOG层（77E）覆盖在MOSFET（72）上。 通过沉积铂的层（81），退火，沉积包括层状超晶格材料的中间层（84），退火，沉积铂的第二层（84），然后对电容器（80）进行构图，形成电容器（80） ）。 沉积另一个SOG层（86），接触孔（106,107）到MOSFET（72）和电容器（80）被部分打开，SOG（86）退火，接触孔（106,107）被完全打开 ，并沉积Pt / Ti / PtSi布线层（88,288）。

公开(公告)号：WO1996027192A1

公开(公告)日：1996-09-06

申请号：PCT/US1996002288

申请日：1996-02-27

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  WATANABE, Hitoshi ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

IPC: G11C11/22

CPC classification number: G11C11/22 ,  G11C11/223 ,  G11C11/2293

Abstract: A method and apparatus for programming ferroelectric memory cells (200, 600) which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices (202) associated with the memory cells such as ferroelectric capacitors (202) and transistors (602). Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material (608) thereby increasing the useful life of ferroelectric memory cells (200, 600). Methods and apparatus for producing a signal pulse duty cycle in the range 2-30 % is disclosed and shown to improve the useful life of the ferroelectric material (608).

Abstract translation: 一种用于编程铁电存储器单元（200,600）的方法和装置，其减小与诸如铁电电容器（202）和晶体管（602）的存储单元相关联的铁电元件（202）的开关极化的极化率疲劳效应。 显示与用于切换铁电体器件极化的信号相关联的脉冲宽度占空比的改变，以降低铁电材料（608）的极化率疲劳，从而增加铁电存储器单元（200,600）的使用寿命。 公开并示出了用于产生2-30％范围内的信号脉冲占空比的方法和装置，以改善铁电材料（608）的使用寿命。

公开(公告)号：WO1996015537A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014611

申请日：1995-11-07

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  WATANABE, Hitoshi ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A method and apparatus for programming ferroelectric memory cells (100, 200) which reduce fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors (102, 202) and transistors (1002). Alteration of the rise and fall times associated with signals used to switch ferroelectric device polarization reduces fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), reduces fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform (322), a Gaussian signal waveform (422), and a waveform (522) having exponential rise anf fall times are disclosed.

Abstract translation: 一种用于编程铁电存储器单元（100,200）的方法和装置，其减少与诸如铁电电容器（102,202）和晶体管（1002）之类的存储单元相关联的铁电元件的开关极化的疲劳效应。 与用于切换铁电体器件极化的信号相关联的上升和下降时间的改变降低了铁电材料的疲劳，从而增加了铁电存储器单元的使用寿命。 降低上升和下降时间以及信号电平上升和下降的速率（信号形状）可以降低铁电元件开关极化的疲劳效应。 公开了用于产生具有指数上升和下降时间的三角形（“锯齿”）信号波形（322），高斯信号波形（422）和波形（522）的方法和装置。

公开(公告)号：WO1995027982A1

公开(公告)日：1995-10-19

申请号：PCT/US1995003758

申请日：1995-03-30

Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD

Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD ,  MCMILLAN, Larry, D. ,  MIHARA, Takashi ,  YOSHIMORI, Hiroyuki ,  GREGORY, John, W. ,  PAZ DE ARAUJO, Carlos, A.

IPC: G11C11/22

CPC classification number: G11C11/22 ,  G11C11/223

Abstract: An integrated memory unit (12, 600) includes a capacitor (30, 30A), a transistor (32, 32A), and saturation means (29, 25, 14, 62, 43, 15, 61; 71A, 72A) for polarizing the ferroelectric material (50, 74) to saturation with a voltage of less than 10 volts. One electrode (47, 49A) of the capacitor and the transistor gate (33, 33A) are the same conductive member. The other electrode may be formed by extensions (71A, 72A) of the transistor source (71) and drain (77) underlying the gate (33A). The capacitor (230, 30A) has a capacitance Cf, and an area Af, and the transistor (232, 32A) forms a gate capacitor (233, 255, 266) having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a. The ferroelectric material (250, 74) has a dielectric constant ELEMENT f and the gate insulator (268, 86) has a dielectric constant ELEMENT g. The memory unit has the parametric relationships: Cf /= 2a, and ELEMENT g >/= ELEMENT f/8.

Abstract translation: 集成存储器单元（12,600）包括电容器（30,30A），晶体管（32,32A）和用于偏振的饱和装置（29,25,14,62,43,15,61,71A，72A） 铁电材料（50,74）以小于10伏特的电压饱和。 电容器和晶体管栅极（33,33A）的一个电极（47,49A）是相同的导电构件。 另一个电极可以由晶体管源极（71）的延伸部（71A，72A）和栅极（33A）下方的漏极（77）形成。 电容器（230,30A）具有电容Cf和区域Af，并且晶体管（232,32A）形成具有面积Ag和栅极电容Cg的栅极电容器（233,255,266），栅极重叠b ，以及频道深度a。 铁电材料（250,74）具有介电常数ELEMENT f，并且栅极绝缘体（268,86）具有介电常数ELEMENT g。 存储单元具有参数关系：Cf <5×Cg，Af / = 2a和ELEMENT g> / = ELEMENT f / 8。