中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

46 records (took 0.02 seconds)

    FERROELECTRIC MEMORY
    3.
    发明申请
    FERROELECTRIC MEMORY 审中-公开
    电磁记忆

    公开(公告)号：WO1996013860A1

    公开(公告)日：1996-05-09

    申请号：PCT/US1995013379

    申请日：1995-10-26

    Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

    Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  WATANABE, Hitoshi ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  McMILLAN, Larry, D.

    IPC: H01L27/115

    CPC classification number: H01L27/11502 ,  G11C11/22

    Abstract: A non-volatile integrated circuit memory (10, 11, 100, 200) in which the memory cell (10, 11) includes a first transistor gate (19, 36) overlying a first channel region (44A), a ferroelectric material (48) overlying a second channel region (44B), and a second transistor gate (23, 37) overlying a third channel region (44C). The channel regions (44A, 44B, 44C) are connected in series, and preferably are contiguous portions of a single semiconducting channel (44). The first channel (44A) is connected to a plate voltage that is 20 % to 50 % of the coercive voltage of the ferroelectric material. A sense amplifier (110) is connected to the third channel region (44C) via a bit line (108). The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.

    Abstract translation: 一种非易失性集成电路存储器（10,11,100,200），其中存储单元（10,11）包括覆盖第一沟道区（44A）的第一晶体管栅极（19,36），铁电材料（48） ）覆盖第二沟道区（44B），以及覆盖第三沟道区（44C）的第二晶体管栅极（23,37）。 沟道区域（44A，44B，44C）串联连接，优选地是单个半导体沟道（44）的邻接部分。 第一通道（44A）与铁电体的矫顽电压的20％〜50％的板电压连接。 读出放大器（110）经由位线（108）连接到第三通道区域（44C）。 在读出逻辑“1”状态之后，位线的上升通过在读出放大器上升之前关闭第三通道来防止铁电材料的干扰。

    ZnO THIN-FILM VARISTORS AND METHOD OF MAKING THE SAME
    5.
    发明申请
    ZnO THIN-FILM VARISTORS AND METHOD OF MAKING THE SAME 审中-公开
    ZnO薄膜变压器及其制造方法

    公开(公告)号：WO1996029712A1

    公开(公告)日：1996-09-26

    申请号：PCT/US1996003519

    申请日：1996-03-14

    Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

    Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  ITO, Takeshi ,  HIRAIDE, Shuzo ,  SCOTT, Michael, C. ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

    IPC: H01C07/10

    CPC classification number: C23C18/1216 ,  C23C16/45561 ,  C23C18/1225 ,  C23C18/1295 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01C7/1013 ,  H01C7/112 ,  H01C17/075 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55

    Abstract: A thin-film zinc oxide varistor (10) for use in integrated circuits and the like is produced by applying a polyoxyalkylated metal complex, such as a metal alkoxycarboxylate, to a substrate (12, 14, and 16) for the formation of a dried non-ohmic layer (18). The method of production includes the steps of providing a substrate and a precursor solution including a polyoxyalkylated zinc complex (P22, P24), coating a portion of the substrate with the precursor solution (P26), drying the coated substrate (P32), and crystallizing the dried thin-film zinc oxide layer (P30). The resultant crystalline zinc oxide varistor layer (18) may be doped with bismuth, yttrium, praseodymium, cobalt, antimony, manganese, silicon, chromium, titanium, potassium, dysprosium, cesium, cerium, and iron to provide a non-ohmic varistor. The varistor layer (10) is annealed at a temperature ranging from about 400 to about 1000 DEG C to provide a layer having a thickness ranging from about 50 nanometers to about 500 nanometers and an average grain size diameter less than about 200 nanometers.

    Abstract translation: 用于集成电路等的薄膜氧化锌变阻器（10）通过将诸如金属烷氧基羧酸盐的聚氧化烷基化金属络合物施加到基底（12,14和16）上来制备，以形成干燥 非欧姆层（18）。 制造方法包括以下步骤：提供包含聚氧化烷基化锌络合物（P22，P24）的基材和前体溶液，用前体溶液（P26）涂布基材的一部分，干燥涂布的基材（P32），使结晶 干燥的薄膜氧化锌层（P30）。 所得结晶氧化锌变阻器层（18）可掺杂铋，钇，镨，钴，锑，锰，硅，铬，钛，​​钾，镝，铯，铈和铁，以提供非欧姆变阻器。 压敏电阻层（10）在约400至约1000℃的温度下退火，以提供厚度范围为约50纳米至约500纳米，平均粒径直径小于约200纳米的层。

    METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS
    6.
    发明申请
    METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS 审中-公开
    在电磁记忆元件中减少疲劳的方法和装置

    公开(公告)号：WO1996027192A1

    公开(公告)日：1996-09-06

    申请号：PCT/US1996002288

    申请日：1996-02-27

    Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

    Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  WATANABE, Hitoshi ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

    IPC: G11C11/22

    CPC classification number: G11C11/22 ,  G11C11/223 ,  G11C11/2293

    Abstract: A method and apparatus for programming ferroelectric memory cells (200, 600) which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices (202) associated with the memory cells such as ferroelectric capacitors (202) and transistors (602). Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material (608) thereby increasing the useful life of ferroelectric memory cells (200, 600). Methods and apparatus for producing a signal pulse duty cycle in the range 2-30 % is disclosed and shown to improve the useful life of the ferroelectric material (608).

    Abstract translation: 一种用于编程铁电存储器单元（200,600）的方法和装置，其减小与诸如铁电电容器（202）和晶体管（602）的存储单元相关联的铁电元件（202）的开关极化的极化率疲劳效应。 显示与用于切换铁电体器件极化的信号相关联的脉冲宽度占空比的改变，以降低铁电材料（608）的极化率疲劳，从而增加铁电存储器单元（200,600）的使用寿命。 公开并示出了用于产生2-30％范围内的信号脉冲占空比的方法和装置，以改善铁电材料（608）的使用寿命。

    METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS
    7.
    发明申请
    METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS 审中-公开
    在电磁记忆元件中减少疲劳的方法和装置

    公开(公告)号：WO1996015537A1

    公开(公告)日：1996-05-23

    申请号：PCT/US1995014611

    申请日：1995-11-07

    Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

    Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  WATANABE, Hitoshi ,  YOSHIMORI, Hiroyuki ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

    IPC: G11C11/22

    CPC classification number: G11C11/22

    Abstract: A method and apparatus for programming ferroelectric memory cells (100, 200) which reduce fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors (102, 202) and transistors (1002). Alteration of the rise and fall times associated with signals used to switch ferroelectric device polarization reduces fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), reduces fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform (322), a Gaussian signal waveform (422), and a waveform (522) having exponential rise anf fall times are disclosed.

    Abstract translation: 一种用于编程铁电存储器单元（100,200）的方法和装置，其减少与诸如铁电电容器（102,202）和晶体管（1002）之类的存储单元相关联的铁电元件的开关极化的疲劳效应。 与用于切换铁电体器件极化的信号相关联的上升和下降时间的改变降低了铁电材料的疲劳，从而增加了铁电存储器单元的使用寿命。 降低上升和下降时间以及信号电平上升和下降的速率（信号形状）可以降低铁电元件开关极化的疲劳效应。 公开了用于产生具有指数上升和下降时间的三角形（“锯齿”）信号波形（322），高斯信号波形（422）和波形（522）的方法和装置。

    NON-VOLATILE MEMORY
    8.
    发明申请
    NON-VOLATILE MEMORY 审中-公开
    非易失性存储器

    公开(公告)号：WO1995027982A1

    公开(公告)日：1995-10-19

    申请号：PCT/US1995003758

    申请日：1995-03-30

    Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD

    Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD ,  MCMILLAN, Larry, D. ,  MIHARA, Takashi ,  YOSHIMORI, Hiroyuki ,  GREGORY, John, W. ,  PAZ DE ARAUJO, Carlos, A.

    IPC: G11C11/22

    CPC classification number: G11C11/22 ,  G11C11/223

    Abstract: An integrated memory unit (12, 600) includes a capacitor (30, 30A), a transistor (32, 32A), and saturation means (29, 25, 14, 62, 43, 15, 61; 71A, 72A) for polarizing the ferroelectric material (50, 74) to saturation with a voltage of less than 10 volts. One electrode (47, 49A) of the capacitor and the transistor gate (33, 33A) are the same conductive member. The other electrode may be formed by extensions (71A, 72A) of the transistor source (71) and drain (77) underlying the gate (33A). The capacitor (230, 30A) has a capacitance Cf, and an area Af, and the transistor (232, 32A) forms a gate capacitor (233, 255, 266) having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a. The ferroelectric material (250, 74) has a dielectric constant ELEMENT f and the gate insulator (268, 86) has a dielectric constant ELEMENT g. The memory unit has the parametric relationships: Cf /= 2a, and ELEMENT g >/= ELEMENT f/8.

    Abstract translation: 集成存储器单元（12,600）包括电容器（30,30A），晶体管（32,32A）和用于偏振的饱和装置（29,25,14,62,43,15,61,71A，72A） 铁电材料（50,74）以小于10伏特的电压饱和。 电容器和晶体管栅极（33,33A）的一个电极（47,49A）是相同的导电构件。 另一个电极可以由晶体管源极（71）的延伸部（71A，72A）和栅极（33A）下方的漏极（77）形成。 电容器（230,30A）具有电容Cf和区域Af，并且晶体管（232,32A）形成具有面积Ag和栅极电容Cg的栅极电容器（233,255,266），栅极重叠b ，以及频道深度a。 铁电材料（250,74）具有介电常数ELEMENT f，并且栅极绝缘体（268,86）具有介电常数ELEMENT g。 存储单元具有参数关系：Cf <5×Cg，Af / = 2a和ELEMENT g> / = ELEMENT f / 8。

    NON-VOLATILE MEMORY
    10.
    发明申请
    NON-VOLATILE MEMORY 审中-公开
    非易失性存储器

    公开(公告)号：WO1995002883A1

    公开(公告)日：1995-01-26

    申请号：PCT/US1994007403

    申请日：1994-06-30

    Applicant: SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD.

    Inventor： SYMETRIX CORPORATION ,  OLYMPUS OPTICAL CO., LTD. ,  MIHARA, Takashi ,  PAZ DE ARAUJO, Carlos, A. ,  MCMILLAN, Larry, D.

    IPC: G11C11/22

    CPC classification number: G11C11/22

    Abstract: A ferroelectric, non-volatile memory (336) includes a constant voltage source (85), a bit line (79), a memory cell (70) having a first ferroelectric capacitor (76) connected between the bit line (79) and the constant voltage source (85), a source (105) of a reference voltage, and a latch (74) connected between the bit line (79) and the reference voltage source (105). The latch (74) drives the bit line (79) to the same logic state as the ferroelectric capacitor (76) to read and rewrite the capacitor (76) in a single operation. The reference voltage is between QI/CD and QSW/CD + QI/CD, where QI is the linear capacitance of said first ferroelectric capacitor (76), CD is the capacitance of said bit line (79), and QSW is the switching charge of said first ferroelectric capacitor (76). In one embodiment, the reference voltage is provided by a ferroelectric dummy capacitor (141) having an area smaller than the area of the first capacitor (128) but greater than 1/2 the area of the first capacitor (128).

    Abstract translation: 铁电非易失性存储器（336）包括恒压源（85），位线（79），存储单元（70），其具有连接在所述位线（79）和所述第一铁电电容器 恒压源（85），参考电压源（105）和连接在位线（79）和参考电压源（105）之间的锁存器（74）。 锁存器（74）将位线（79）驱动到与铁电电容器（76）相同的逻辑状态，以便在单次操作中读取和重写电容器（76）。 参考电压在QI / CD和QSW / CD + QI / CD之间，其中QI是所述第一铁电电容器（76）的线性电容，CD是所述位线（79）的电容，QSW是开关电荷 的所述第一铁电电容器（76）。 在一个实施例中，参考电压由具有小于第一电容器（128）的面积但大于第一电容器（128）的面积的1/2的铁电虚拟电容器（141）提供。

Patent Agency Ranking