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    DRAM TRENCH CAPACITOR AND METHOD OF MAKING THE SAME
    2.
    发明申请
    DRAM TRENCH CAPACITOR AND METHOD OF MAKING THE SAME 审中-公开
    DRAM TRENCH电容器及其制造方法

    公开(公告)号：WO03017336A3

    公开(公告)日：2003-09-04

    申请号：PCT/US0225680

    申请日：2002-08-13

    Applicant: AMBERWAVE SYSTEMS CORP

    Inventor： BULSARA MAYANK ,  CURRIE MATTHEW T ,  LOCHTEFELD ANTHONY J

    IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

    CPC classification number: H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/40 ,  H01L29/1054 ,  H01L29/7849 ,  H01L29/945

    Abstract: In accordanse with the present invention, DRAM trench capacitors are formed in substrates including materials other than Si, such as SiGe. These materials may be relaxed or strained, and may have dislocation defects. In one aspect, therefore, the invention features a method for forming a trench capacitor in a semiconductor substrate. A trench is defined extending into the semiconductor substrate from a top surface of the substrate. A first conductive material is deposited in the trench to define an outer plate, and an insulating layer is formed on the outer plate. A second conductive material is deposited in the trench to define an inner plate. Trench capacitors formed in accordance with the present invention may be utilized in conventional CMOS logic circuits. A DRAM trench capacitor (600) is formed on a semiconductor substrate (610) in accordance with any of the methods described above. Semiconductor substrate (610) includes a substrate (612) formed of, e.g., Si, and a layer (614) including, for example, graded and relayed and relaxed SiGe layers. A tensilely strained layer (616) is disposed over layer (614). DRAM trench capacitor (600) is in electrical communication with access transistor (620). A CMOS logic circuit (630) is also formed on semiconductor substrate (610). CMOS logic circuit (630) may include an NMOS transistor (640) and a PMOS transistor (650), with each transistor having a channel (660, 670) disposed in tensilely strained layer (616).

    Abstract translation: 根据本发明，DRAM沟槽电容器形成在包括除Si之外的材料的衬底中，例如SiGe。 这些材料可能松弛或变形，并且可能具有位错缺陷。 因此，一方面，本发明的特征在于在半导体衬底中形成沟槽电容器的方法。 限定从衬底的顶表面延伸到半导体衬底中的沟槽。 第一导电材料沉积在沟槽中以限定外板，并且在外板上形成绝缘层。 第二导电材料沉积在沟槽中以限定内板。 根据本发明形成的沟槽电容器可以用于传统的CMOS逻辑电路中。 根据上述任何一种方法，在半导体衬底（610）上形成DRAM沟槽电容器（600）。 半导体衬底（610）包括由例如Si形成的衬底（612）和包括例如渐变和中继且弛豫的SiGe层的层（614）。 拉伸应变层（616）设置在层（614）之上。 DRAM沟槽电容器（600）与存取晶体管（620）电连通。 CMOS逻辑电路（630）也形成在半导体衬底（610）上。 CMOS逻辑电路（630）可以包括NMOS晶体管（640）和PMOS晶体管（650），每个晶体管具有设置在拉伸应变层（616）中的沟道（660,670）。

    METHODS FOR PRESERVING STRAINED SEMICONDUCTOR LAYERS DURING OXIDE LAYER FORMATION
    3.
    发明申请
    METHODS FOR PRESERVING STRAINED SEMICONDUCTOR LAYERS DURING OXIDE LAYER FORMATION 审中-公开
    用于在氧化层形成期间保持应变半导体层的方法

    公开(公告)号：WO2004102635A3

    公开(公告)日：2005-06-02

    申请号：PCT/US0334576

    申请日：2003-10-30

    Applicant: AMBERWAVE SYSTEMS CORP

    Inventor： CURRIE MATTHEW T ,  LOCHTEFELD ANTHONY J

    IPC: H01L21/20 ,  H01L21/265 ,  H01L21/308 ,  H01L21/316

    CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02538 ,  H01L21/02664 ,  H01L21/2652 ,  H01L21/823807 ,  H01L29/1054

    Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

    Abstract translation: 避免在Si / SiGe异质结构基晶片中消耗不希望的大量表面材料的氧化方法代替了各种中间CMOS热氧化步骤。 首先，通过使用氧化物沉积方法，可以形成少量或不消耗表面硅的任意厚的氧化物。 这些氧化物，例如筛选氧化物和氧化垫，通过沉积到表面层上而不是与表面层反应并消耗而形成。 或者，氧化物沉积之前是短时间的热氧化步骤，例如快速热氧化。 这里，短的热氧化消耗很少的表面Si，并且Si /氧化物界面是高质量的。 然后可以通过沉积将氧化物增稠至所需的最终厚度。 此外，薄的热氧化物可以用作阻挡层，以防止与随后的氧化物沉积相关的污染。

    METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING
    8.
    发明申请
    METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING 审中-公开
    CMOS工艺过程中保护半导体衬底层的方法

    公开(公告)号：WO2004102635A9

    公开(公告)日：2005-02-03

    申请号：PCT/US0334576

    申请日：2003-10-30

    Applicant: AMBERWAVE SYSTEMS CORP

    Inventor： CURRIE MATTHEW T ,  LOCHTEFELD ANTHONY J

    IPC: H01L21/20 ,  H01L21/265 ,  H01L21/00

    CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02538 ,  H01L21/02664 ,  H01L21/2652 ,  H01L21/823807 ,  H01L29/1054

    Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

    Abstract translation: 避免在Si / SiGe异质结构基晶片中消耗不希望的大量表面材料的氧化方法代替了各种中间CMOS热氧化步骤。 首先，通过使用氧化物沉积方法，可以形成少量或不消耗表面硅的任意厚的氧化物。 这些氧化物，例如筛选氧化物和氧化垫，通过沉积到表面层上而不是与表面层反应并消耗而形成。 或者，氧化物沉积之前是短时间的热氧化步骤，例如快速热氧化。 这里，短的热氧化消耗很少的表面Si，并且Si /氧化物界面是高质量的。 然后可以通过沉积将氧化物增稠至所需的最终厚度。 此外，薄的热氧化物可以用作阻挡层，以防止与随后的氧化物沉积相关的污染。

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