公开(公告)号：WO2015191842A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/035311

申请日：2015-06-11

Applicant: DECA TECHNOLOGIES INC.

Inventor： SCANLAN, Christopher, M. ,  BISHOP, Craig

IPC: H05K3/02 ,  H01L21/48

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3135 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/0217 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/117 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8212 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline.

Abstract translation: 描述了一种用于具有动态通道限幅的镶板包装的自适应图案化的半导体器件和方法。 可以形成包括围绕多个半导体管芯设置的封装材料的面板。 可以测量面板内的多个半导体管芯中的每一个的实际位置。 可以形成包括与多个半导体管芯中的每一个的实际位置对准的第一捕获垫的导电再分配层（RDL）。 可以形成至少部分地布置在第一捕获垫上并且与多个半导体封装中的每一个的封装轮廓对准的多个第二捕获焊盘。 可以调整多个导电通孔的标称占地面积，以解决每个半导体管芯与其相应的封装外形之间的错位。