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    THERMALLY ENHANCED FULLY MOLDED FAN-OUT MODULE
    1.
    发明申请
    THERMALLY ENHANCED FULLY MOLDED FAN-OUT MODULE 审中-公开
    热成型完全模制的风扇模块

    公开(公告)号：WO2017049269A1

    公开(公告)日：2017-03-23

    申请号：PCT/US2016/052436

    申请日：2016-09-19

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： SCANLAN, Christopher, M.

    IPC: H01L21/78

    CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/09 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511

    Abstract: A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can be mounted face up to the temporary carrier such that back surfaces of the first semiconductor die and the second semiconductor die are depressed within the adhesive. An embedded die panel can be formed by encapsulating at least four sides surfaces and an active surface of the first semiconductor die, the second semiconductor die, and side surfaces of the conductive interconnects in a single step. The conductive interconnects of the first semiconductor die and the second semiconductor die can be interconnected without a silicon interposer by forming a fine-pitch build-up interconnect structure over the embedded die panel to form at least one molded core unit. The at least one molded core unit can be mounted to an organic multi-layer substrate.

    Abstract translation: 制造半导体器件的方法可以包括提供具有粘合剂的临时载体。 可以将第一半导体管芯和第二半导体管芯面朝上安装到临时载体上，使得第一半导体管芯和第二半导体管芯的背面在粘合剂内被压下。 可以通过在一个步骤中封装至少四个侧表面和第一半导体管芯，第二半导体管芯和导电互连的侧表面的有源表面来形成嵌入式裸片。 第一半导体管芯和第二半导体管芯的导电互连可以通过在嵌入的模具面板上形成微细间距建立互连结构而形成至少一个模制的核心单元，而不需要通过硅插入器来互连。 所述至少一个成型芯单元可以安装到有机多层基板上。

    SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT 审中-公开
    半导体器件和单元特定逐步对准方法

    公开(公告)号：WO2018053441A1

    公开(公告)日：2018-03-22

    申请号：PCT/US2017/052095

    申请日：2017-09-18

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： BISHOP, Craig ,  SCANLAN, Christopher, M.

    IPC: H01L21/66

    Abstract: A semiconductor device and method can comprise measuring a true position of each of a plurality of semiconductor die within an embedded die panel and determining a total radial shift of each of the plurality of semiconductor die. The total radial shift of each of the plurality of semiconductor die can be distributed to two or more layers for each of the plurality of semiconductor die by assigning a portion of the total radial shift to each of the layers according to a priority list to form a distributed radial shift for each of the layers. A transformation for each of the layers for each of the plurality of semiconductor die can be transformed using the distributed radial shift for each of the layers. A unit specific pattern can be formed over each of the plurality of semiconductor die with the transformation for each of the layers.

    Abstract translation: 半导体器件和方法可以包括测量多个半导体裸片中的每一个在嵌入式裸片面板内的真实位置并且确定多个半导体裸片中的每一个的总径向偏移。 通过根据优先级列表将全部径向偏移的一部分分配给每个层，可以将多个半导体管芯中的每一个的全部径向偏移分配到用于多个半导体管芯中的每一个的两个或更多个层以形成 为每个层分布径向偏移。 对于多个半导体管芯中的每个半导体管芯的每个层的变换可以使用用于每个层的分布式径向偏移来变换。 通过每层的转换可以在多个半导体管芯中的每一个上形成单元特定图案。

    FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE
    6.
    发明申请
    FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE 审中-公开
    完全成型的微型化半导体模块

    公开(公告)号：WO2017087899A1

    公开(公告)日：2017-05-26

    申请号：PCT/US2016/062940

    申请日：2016-11-18

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： SCANLAN, Christopher, M. ,  OLSON, Timothy, L.

    IPC: H01L21/77 ,  H01L23/538

    CPC classification number: H01L21/77 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511

    Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

    Abstract translation: 半导体模块可以包括完全模制的基座部分，该基座部分包括平坦表面，该平坦表面还包括半导体管芯，该半导体管芯包括接触焊盘，耦合到接触焊盘并延伸到平坦表面的导电柱以及密封剂材料 设置在有源表面，四个侧表面上以及导电柱周围，其中导电柱的端部从完全模制的基底部分的平坦表面处的密封剂材料暴露。 包括布线层的增层互连结构可以设置在完全模制的基部上。 可光成像的焊接掩模材料可以设置在布线层上并且包括开口以形成电耦合到半导体管芯和导电柱的表面安装器件（SMD）焊盘。 SMD元件可通过表面贴装技术（SMT）与SMD焊盘电耦合。

    FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE
    7.
    发明申请
    FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE 审中-公开
    包装设备上完全成型外围包装

    公开(公告)号：WO2017087427A1

    公开(公告)日：2017-05-26

    申请号：PCT/US2016/062112

    申请日：2016-11-15

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： SCANLAN, Christopher, M. ,  ROGERS, William, Boyd ,  BISHOP, Craig

    IPC: H01L21/768 ,  H01L21/50

    CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/97

    Abstract: A method of making a semiconductor device can include providing a temporary carrier with a semiconductor die mounting site, and forming conductive interconnects over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted at the semiconductor die mounting site. The conductive interconnects and semiconductor die can be encapsulated with mold compound. First ends of the conductive interconnects can be exposed. The temporary carrier can be removed to expose second ends of the conductive interconnects opposite the first ends of the conductive interconnects. The conductive interconnects can be etched to recess the second ends of the conductive interconnects with respect to the mold compound. The conductive interconnects can comprise a first portion, a second portion, and an etch stop layer disposed between the first portion and the second portion.

    Abstract translation: 制造半导体器件的方法可以包括提供具有半导体管芯安装部位的临时载体，以及在半导体管芯安装部位的外围中的临时载体上形成导电互连。 半导体管芯可以安装在半导体管芯安装地点。 导电互连和半导体管芯可以用模塑化合物封装。 导电互连的第一端可以暴露。 临时载体可被移除以暴露与导电互连的第一端相对的导电互连的第二端。 导电互连可以被蚀刻以使导电互连的第二端相对于模制化合物凹陷。 导电互连可以包括第一部分，第二部分和设置在第一部分和第二部分之间的蚀刻停止层。

    FULLY MOLDED SEMICONDUCTOR PACKAGE FOR POWER DEVICES AND METHOD OF MAKING THE SAME
    9.
    发明申请
    FULLY MOLDED SEMICONDUCTOR PACKAGE FOR POWER DEVICES AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：WO2019209809A1

    公开(公告)日：2019-10-31

    申请号：PCT/US2019/028693

    申请日：2019-04-23

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： OLSON, Timothy, L. ,  SCANLAN, Christopher, M.

    IPC: H01L21/56 ,  H01L21/78

    Abstract: A method of making a semiconductor device can include providing a semiconductor die comprising a front surface comprising a gate pad and a source pad, the semiconductor die further comprising a back surface opposite the front surface, the back surface comprising a drain. A gate stud may be formed over and coupled to the gate pad. A source stud may be formed over and coupled to the source pad. An encapsulant may be formed over the semiconductor die. A through mold interconnect may extend between opposing first and second surfaces of the encapsulant. An RDL may be coupled to the gate stud, the source stud, and to the through mold interconnect. A land pad may be formed over the back surface of the semiconductor die and be coupled to the drain after singulating the semiconductor die from its native wafer and after forming the encapsulant over the semiconductor die.

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