公开(公告)号：WO2023278093A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/031793

申请日：2022-06-01

Applicant: QUALCOMM INCORPORATED

Inventor： XIE, Biancun ,  PANDEY, Shree Krishna

IPC: H01L23/50 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/18 ,  H01L25/50 ,  H01L27/013 ,  H01L28/40

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.

公开(公告)号：WO2021118803A2

公开(公告)日：2021-06-17

申请号：PCT/US2020/061987

申请日：2020-11-24

Applicant: APPLE INC.

Inventor： LUPO, Pierpaolo ,  KANI, Bilal Mohamed Ibrahim ,  RENJAN, Kishore N. ,  KIM, Kyusang ,  VADEENTAVIDA, Manoj

IPC: G01K7/18 ,  G01K7/02 ,  G01K13/20 ,  A61B5/01 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/34 ,  H01L23/498 ,  H01L23/538 ,  G01J5/00 ,  H05K1/18 ,  H04R1/10 ,  A61B5/6815 ,  G01J5/0011 ,  G01J5/0025 ,  G01J5/0215 ,  G01J5/04 ,  G01J5/0862 ,  G01J5/0875 ,  G01J5/12 ,  G01K1/08 ,  G01K7/16 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/568 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2224/2413 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19106 ,  H04R1/1016 ,  H05K1/185 ,  H05K2201/10151

Abstract: Temperature sensor packages and methods of fabrication are described. The temperature sensor packages in accordance with embodiments may be rigid or flexible. In some embodiments the temperature sensor packages are configured for touch sensing, and include an electrically conductive sensor pattern such as a thermocouple or resistance temperature detector (RTD) pattern. In some embodiments, the temperature sensor packages are configured for non-contact sensing an include an embedded transducer.

公开(公告)号：WO2021252100A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/030697

申请日：2021-05-04

Applicant: QUALCOMM INCORPORATED

Inventor： LAN, Je-Hsiung ,  KIM, Jonghae ,  DUTTA, Ranadeep

IPC: H01L23/522 ,  H01F17/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L21/4882 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L23/3128 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2924/1421

Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

公开(公告)号：WO2021076872A2

公开(公告)日：2021-04-22

申请号：PCT/US2020/055953

申请日：2020-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Yangyang ,  HOLMES, John ,  ZHANG, Xuefeng ,  HE, Dongming

IPC: H01L23/485 ,  H01L21/60 ,  G06T7/00 ,  G06T7/0006 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/15747

Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

公开(公告)号：WO2021202358A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/024623

申请日：2021-03-29

Applicant: CREE, INC.

Inventor： NOORI, Basim ,  MARBELL, Marvin ,  MU, Qianli ,  LIM, Kwangmo Chris ,  WATTS, Michael E. ,  BOKATIUS, Mario ,  KIM, Jangheon

IPC: H01L29/417 ,  H01L23/66 ,  H01L25/16 ,  H03F1/00 ,  H03F3/00 ,  H01L23/00 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/08225 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/42 ,  H01L24/81 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/778 ,  H01L29/7786 ,  H03F1/565 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03F3/193 ,  H03F3/195

Abstract: RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

公开(公告)号：WO2020117431A2

公开(公告)日：2020-06-11

申请号：PCT/US2019/060916

申请日：2019-11-12

Applicant: GOOGLE LLC

Inventor： KWON, Woon, Seong ,  URATA, Ryohei ,  KANG, Teckgyu

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/58 ,  H01L21/481 ,  H01L21/563 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83855 ,  H01L23/293 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5381 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/15153

Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device includes a first substrate layer (220) and a second substrate layer (210) adhered to the first substrate layer (220) such that a portion of the top surface of the first substrate layer (220) is exposed to define a bottom of a cavity (230), and an edge of the second substrate layer (210) adjacent to the exposed top surface of the first substrate layer (220) defines an edge of the cavity (230). The device includes an integrated circuit die (240) adhered to the exposed top surface of first substrate layer (220) with a liquid adhesive. The first substrate layer (220) can define a trench (260a, 260b) in the bottom of the cavity (230) between a region of the integrated circuit die (240) and the edge of the cavity (230) such that the trench (260a, 260b) can receive bleed-out of the liquid adhesive from between the integrated circuit die (240) and the top surface of the first substrate layer (220).

公开(公告)号：WO2022182938A2

公开(公告)日：2022-09-01

申请号：PCT/US2022/017817

申请日：2022-02-25

Applicant: MARVELL ASIA PTE LTD ,  GRAF, Richard ,  ENGLAND, Luke ,  NAYINI, Manish ,  PATEL, Janak G.

Inventor： GRAF, Richard ,  ENGLAND, Luke ,  NAYINI, Manish ,  PATEL, Janak G.

IPC: H01L21/683 ,  H01L23/36 ,  H01L23/538 ,  H01L21/67 ,  H01L21/6835 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/92225 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3511

Abstract: A method for assembling at least one stacked substrate package, each stacked substrate package includes binding a laminated base substrate (104), configured to route interconnections between circuitry on a first surface of the laminated base substrate and circuitry on a second surface of the laminated base substrate, to a surface of a rigid carrier (102) to prevent warping of the laminated base substrate (104). Each base substrate is coupled to at least one dielectric build-up substrate (106), which is configured to route integrated interconnections between a top surface and a bottom surface of the dielectric build-up substrate, to the laminated base substrate (104). At least one integrated circuit die (108) is coupled to the at least one dielectric build-up substrate (106), and then the carrier (102) is released from the laminated base substrate (104) to form an assembled stacked substrate package. Also, multiple stacked substrate packages may be assembled in parallel on one carrier.

公开(公告)号：WO2021252104A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/030839

申请日：2021-05-05

Applicant: QUALCOMM INCORPORATED

Inventor： PATIL, Aniket ,  WE, Hong Bok ,  KANG, Kuiwon

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76838 ,  H01L21/76895 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/16151 ,  H01L2224/24151 ,  H01L2224/821 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/528 ,  H01L24/24 ,  H01L24/25 ,  H01L27/14636 ,  H01L39/2454

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects.

公开(公告)号：WO2022271409A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/031340

申请日：2022-05-27

Applicant: QUALCOMM INCORPORATED

Inventor： ROY, Abinash ,  VEMULA, Lohith Kumar ,  CHAVA, Bharani ,  KIM, Jonghae

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H01G4/232 ,  H01L21/4803 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/642 ,  H01L25/16

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.

公开(公告)号：WO2022229830A1

公开(公告)日：2022-11-03

申请号：PCT/IB2022/053844

申请日：2022-04-26

Applicant: TANGRAM IMAGE SENSOR

Inventor： NI, Yang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/4857 ,  H01L2224/0401 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/114 ,  H01L2224/1148 ,  H01L2224/11612 ,  H01L2224/11616 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13184 ,  H01L2224/16014 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81948 ,  H01L2224/83365 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/01104

Abstract: On propose selon l'invention un procédé de fabrication d'un circuit électronique en technologie C-MOS, le procédé comprenant : (a) une étape de dépôt métallique (200) et de gravure pour former des liaisons métalliques (P, P',...) à un premier niveau dans un substrat, (b) une étape de dépôt d'une couche de matériau diélectrique (110,...) recouvrant les liaisons métalliques, (c) une étape de réalisation de passages traversants (112) dans l'épaisseur du matériau diélectrique, (d) une étape de remplissage de ces passages avec un métal d'interconnexion (300), pour former des vias (V) de connexion entre niveaux, Les étapes (a) à (d) étant répétées pour former des liaisons métalliques (P, P',...) à différents niveaux de profondeurs, reliés par des vias (V) d'interconnexion dans l'épaisseur du circuit, Selon l'invention, le procédé comprend en outre une itération de l'étape (a) pour former simultanément : * un ensemble de d'éléments conducteurs individualisés (PL, P'") aux fins de connexion dudit circuit électronique avec des plots conducteurs homologues d'un autre circuit par rapprochement et pression entre les circuits, et * un ensemble de plots de liaison (PB) pour fils de bonding.