公开(公告)号：WO2022237112A1

公开(公告)日：2022-11-17

申请号：PCT/CN2021/131556

申请日：2021-11-18

Applicant: 苏州东微半导体股份有限公司

Inventor： 龚轶 ,  毛振东 ,  徐真逸 ,  刘磊

IPC: H01L29/66 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/423

Abstract: 本申请属于半导体器件技术领域，公开了一种半导体器件的制造方法，包括：在半导体衬底内形成沟槽；在所述沟槽内形成第一绝缘层和屏蔽栅；对所述第一绝缘层进行刻蚀，在所述沟槽的上部内形成栅极区域；对所述半导体衬底和所述屏蔽栅进行刻蚀以增加所述栅极区域的宽度；进行离子注入，在所述半导体衬底内形成位于所述栅极区域下方的电荷存储区；在所述栅极区域内形成栅介质层和栅极。

公开(公告)号：WO2021167639A1

公开(公告)日：2021-08-26

申请号：PCT/US2020/035566

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： UEDA, Yu ,  SANO, Michiaki ,  CUI, Zhixin ,  YASUDA, Ippei

IPC: H01L27/11563 ,  H01L29/792 ,  H01L21/02

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

公开(公告)号：WO2019046189A1

公开(公告)日：2019-03-07

申请号：PCT/US2018/048138

申请日：2018-08-27

Applicant: CYPRESS SEMICONDUCTOR CORPORATION

Inventor： VARKONY, Roni ,  BETSER, Yoram

IPC: G11C16/12 ,  G11C16/14 ,  H01L27/11563

Abstract: A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently.

公开(公告)号：WO2021217358A1

公开(公告)日：2021-11-04

申请号：PCT/CN2020/087295

申请日：2020-04-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WU, Linchun ,  LI, Shan ,  XIA, Zhiliang ,  ZHANG, Kun ,  ZHOU, Wenxi ,  HUO, Zongliang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/823487 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/41741

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug.

公开(公告)号：WO2021194996A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023535

申请日：2021-03-22

Applicant: HSU, Fu-Chang

Inventor： HSU, Fu-Chang

IPC: H01L27/11551 ,  H01L27/11553 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/1158 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/2273 ,  G11C11/2275 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11206 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/249

Abstract: A three dimensional double-density memory array is disclosed. In an embodiment, a three-dimensional (3D) double density array comprises a string of memory devices that are configured so that a first portion of the memory devices form a first channel and a second portion of the memory devices form a second channel. The array also comprises a plurality of word lines coupled to the string of memory devices. Each word line is coupled to a memory device that forms the first channel and a memory device that forms the second channel. The array also comprises at least one drain select gate that couples the first and second channels to a bit line.

公开(公告)号：WO2017222605A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/018759

申请日：2017-02-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PANG, Liang ,  PACHAMUTHU, Jayavel ,  DONG, Yingda

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11548 ,  H01L27/11563 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/31111 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

Abstract: Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si 3 N 4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO 2 . The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO 2 . The two SiO 2 layers together form a blocking oxide layer.

Abstract translation: 制造具有减小的邻近字线干扰的存储器件的技术以及相应的存储器件。 存储器件包括交替的导电层和介电层的堆叠，其中导电层形成存储器单元的字线或控制栅极。 在一个方面中，避免了由于在制造期间的意外氧化而使控制栅极层四舍五入。 非晶硅层沿存储器孔的侧壁沉积，与控制栅极层相邻。 Si 3 N 4沿非晶硅层沉积并在记忆孔中氧化形成SiO 2。 非晶硅层充当用于控制栅极层的牺牲材料的氧化阻挡层。 随后将非晶硅层氧化以形成SiO 2 2。 两个SiO 2层一起形成阻挡氧化层。

公开(公告)号：WO2023029036A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/116668

申请日：2021-09-06

Applicant: 长江存储科技有限责任公司

Inventor： 杜小龙 ,  高庭庭 ,  夏志良 ,  孙昌志 ,  刘佳裔 ,  刘小欣

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11563

Abstract: 本申请提供了一种三维存储器及其制造方法，该三维存储器包括堆叠结构，堆叠结构包括第一堆叠层和第二堆叠层，第一堆叠层包括交替堆叠的控制栅极层和第一介质层，沿相同的堆叠的方向，第二堆叠层包括交替堆叠的顶部选择栅极层和第二介质层；多个沟道结构，沟道结构贯穿堆叠结构，沟道结构包括电荷存储层，电荷存储层包括沿堆叠的方向间断设置的多个电荷存储部分，电荷存储部分设于相邻的所述第一介质层之间；以及至少一个隔离结构，贯穿顶部选择栅极层且位于相邻的沟道结构之间。本申请实施方式提供三维存储器及制造方法能够维持顶部选择栅切线的工艺窗口不变，减少存储密度损失。

公开(公告)号：WO2021097812A1

公开(公告)日：2021-05-27

申请号：PCT/CN2019/120318

申请日：2019-11-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： LIU, Liheng ,  YANG, Chuan ,  PENG, Shuangshuang

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11563

Abstract: A semiconductor device includes a metal layer and a spacer arranged adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.

公开(公告)号：WO2021035738A1

公开(公告)日：2021-03-04

申请号：PCT/CN2019/103860

申请日：2019-08-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WANG, Qingqing ,  XU, Wei ,  HUANG, Pan ,  YAN, Ping ,  HUO, Zongliang ,  ZHOU, Wenbin

IPC: H01L27/11563 ,  H01L27/11578 ,  H01L27/11568

Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.

公开(公告)号：WO2020171869A1

公开(公告)日：2020-08-27

申请号：PCT/US2019/063472

申请日：2019-11-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： CUI, Zhixin ,  NISHIKAWA, Masatoshi ,  ZHANG, Yanli

IPC: H01L27/11563 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/764

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.