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    Resin filler and multilayer printed wiring board
    91.
    发明公开
    Resin filler and multilayer printed wiring board 失效
    树脂填料和多层印刷线路板

    公开(公告)号：EP1318708A2

    公开(公告)日：2003-06-11

    申请号：EP03004268.3

    申请日：1996-10-23

    Applicant: IBIDEN CO., LTD.

    Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

    IPC: H05K3/46 ,  H05K3/38

    CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

    Abstract: A build-up multilayer printed circuit board in which an interlaminar insulating layer and a conductor layer are alternately laminated on a surface of a wiring substrate (1) having a conductor circuit (4) and a through-hole (9), and the conductor layers are electrically connected to each other through a viahole formed in the interlaminar insulating layer, characterized in that a roughened layer (11) is formed on a conductor surface of an inner wall of the through-hole (9), and a resin filler (10) is filled in a through-hole (9) formed in the wiring substrate (1).

    Abstract translation: 一种积层多层印刷电路板，其中层间绝缘层和导体层交替层叠在具有导体电路（4）和通孔（9）的布线基板（1）的表面上，并且导体 层通过形成在层间绝缘层中的通孔彼此电连接，其特征在于，在通孔（9）的内壁的导体表面上形成粗糙层（11），并且树脂填料（ 10）填充在布线基板（1）中形成的通孔（9）中。

    MULTILAYER PRINTED WIRING BOARD AND PRODUCTION METHOD THEREOF
    94.
    发明公开
    MULTILAYER PRINTED WIRING BOARD AND PRODUCTION METHOD THEREOF 有权
    维多利亚ZU DEREN HERSTELLUNG的MEHRSCHICHTIGE LEITERPLATTE

    公开(公告)号：EP1098558A1

    公开(公告)日：2001-05-09

    申请号：EP99926766.9

    申请日：1999-06-23

    Applicant: IBIDEN CO., LTD.

    Inventor： NISHIWAKI, Yoko ,  NODA, Kouta

    IPC: H05K3/46 ,  H05K3/38

    CPC classification number: H05K3/4626 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/0094 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4602 ,  H05K2201/0108 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1157 ,  Y10T29/49155

    Abstract: A multilayer printed wiring board has such a structure that conductor circuit patterns are formed on a core substrate through interlaminar resin insulating layers and through-holes are formed in the core substrate and a filler is filled in the through-hole. The interlaminar resin insulating layer formed on the substrate is flat and the same kind of roughened layer is formed on the conductor circuit pattern on the substrate over a full surface including a side surface thereof. A cover plated layer is formed just above the through-hole, and the roughened layers are formed on the conductor layer and the conductor circuit pattern located at the same level as the conductor layer over a full surface including side surfaces thereof, and the interlaminar resin insulating layer is formed so as to cover the surfaces of these roughened layers and filled in recess portions between the conductors and flattened on its surface. Thus, it is excellent in the crack resistance under heat cycle condition or the like and does not cause the damage of the cover plated layer.

    Abstract translation: 多层印刷电路板具有通过层间树脂绝缘层在芯基板上形成导体电路图案的结构，并且在芯基板中形成通孔，并且在通孔中填充填料。 形成在基板上的层间树脂绝缘层是平坦的，并且在包括其侧表面的整个表面上的基板上的导体电路图案上形成相同类型的粗糙层。 在通孔的正上方形成覆盖层，在导体层上形成有粗糙层，导体电路图案与导体层位于与包含侧面的整个表面相同的层上，层间树脂 形成绝缘层以覆盖这些粗糙层的表面并填充在导体之间的凹部中并在其表面上变平。 因此，在热循环条件等下的耐龟裂性优异，不会引起覆盖层的损伤。

    Mikrowellen-Streifen-Leitungsanordnung
    97.
    发明公开
    Mikrowellen-Streifen-Leitungsanordnung 失效
    Mikrowellen-Streifen-Leitungsanordnung。

    公开(公告)号：EP0478962A2

    公开(公告)日：1992-04-08

    申请号：EP91114671.0

    申请日：1991-08-30

    Applicant: Rohde & Schwarz GmbH & Co. KG

    Inventor： Szpilok, Waldemar, Dipl.-Ing.

    IPC: H05K3/46 ,  H05K1/00 ,  H01P3/08 ,  H01P1/203

    CPC classification number: H01P3/085 ,  H01P1/2039 ,  H05K1/024 ,  H05K1/144 ,  H05K2201/0715 ,  H05K2201/09881

    Abstract: Bei einer in Triplate-Technik aufgebauten Mikrowellenschaltung (3) ist der Kern (12) der Streifenleitung (4) aus einer Trägerplatte aus Isoliermaterial geformt, der an mindestens zwei Seiten (13,14) mit einer Metallschicht überzogen ist und über ebenfalls aus der Trägerplatte geformte seitlich abstehende schmale Stege (11) aus Isoliermaterial mittels Stützen (15) freitragend zwischen den Leiterplatten (1,2) gehalten ist.

    Abstract translation: 在使用三板技术构造的微波电路中，带状线的芯由介电材料的载体板形成，该介电材料的载体板至少在两侧涂覆有金属层，并以自支撑的方式保持在印刷电路板之间 借助于通过狭窄的电介质材料网的支柱，其横向突出并且同样由载体板形成。

    Integrated circuit packaging using flexible substrate
    98.
    发明公开
    Integrated circuit packaging using flexible substrate 失效
    Integrierte Schaltungseinheit mit flexiblem Substrat。

    公开(公告)号：EP0460822A1

    公开(公告)日：1991-12-11

    申请号：EP91304504.3

    申请日：1991-05-20

    Applicant: International Business Machines Corporation

    Inventor： Frankeny, Jerome Albert ,  Frankeny, Richard Francis ,  Hermann, Karl ,  Imken, Ronald Lann

    IPC: H05K3/36

    CPC classification number: H05K3/429 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/0393 ,  H05K3/445 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09581 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/1438 ,  Y10T29/41

    Abstract: A multilayer, flexible substrate 64 upon which integrated circuit chips 60 can be attached is disclosed. The input/output(I/O) connections 62 from the chip do not radiate outward from the side of the die, but rather extend from a bottom surface. Since the I/O signal lines would not be accessible for testing once the IC chip is mounted on a substrate, each I/O line is extended outward 68 from the IC footprint to an area on the substrate which is accessible. Additionally, an electrical path from each I/O signal port is simultaneously passed through the substrate layers upon which the chip is mounted, thus providing electrical contact of all I/O ports to the underside of the flexible substrate.
    An integrated circuit chip is mounted on this flexible substrate. Since each I/O line is accessible after mounting, the IC chip can be tested prior to mounting on its ultimate carrier. Once tested, the IC chip and the substrate upon which it is mounted are excised from the roll of substrate material. This excised, pretested memory package, which includes both the IC chip and the flexible substrate, can then be mounted directly onto the ultimate carrier either by reflow soldering or direct bonding.

    Abstract translation: 公开了可以连接集成电路芯片60的多层柔性基板64。 来自芯片的输入/输出（I / O）连接62不会从模具的侧面向外辐射，而是从底表面延伸。 由于一旦将IC芯片安装在基板上，I / O信号线将无法进行测试，因此每个I / O线从IC封装向外延伸68，从而可访问基板上的一个区域。 此外，来自每个I / O信号端口的电路同时通过其上安装有芯片的衬底层，从而提供所有I / O端口与柔性衬底的下侧的电接触。 集成电路芯片安装在该柔性基板上。 由于每个I / O线在安装后都可以访问，因此IC芯片可以在安装在其最终载体上之前进行测试。 一旦测试，将IC芯片及其安装在其上的基板从基板材料卷上切下。 包括IC芯片和柔性基板在内的这种预先测试的存储器封装可以通过回流焊接或直接接合直接安装在极限载体上。

    METHOD OF PRODUCING CONDUCTOR CIRCUIT BOARDS
    100.
    发明公开
    METHOD OF PRODUCING CONDUCTOR CIRCUIT BOARDS 失效
    HERSTELLUNG VON PLATTEN MIT ELEKTROSCHALTUNGEN。

    公开(公告)号：EP0258451A1

    公开(公告)日：1988-03-09

    申请号：EP87901645.9

    申请日：1987-02-21

    Applicant: MEIKO ELECTRONICS CO., LTD.

    Inventor： WADA, Tatsuo 4-406, Towdate Bldg. ,  YAMASHITA, Keizo 12-23, Ishida 2-chome ,  TOUYAMA, Tasuku 127-4, Kitawaki ,  YAMAMOTO, Teruaki 11-5, Oguro 2-chome

    IPC: H05K3/20

    CPC classification number: H05K3/205 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/0726 ,  Y10T29/49158

    Abstract: A thin metal layer is formed by electrolysis (S2) maintaining a thickness of 1 to 5 µm on an electrically conductive single-plate substrate having a predetermined coarseness, a resist mask is formed (S3) on the surface of the thin metal layer, and then a conductor circuit is electroformed thereon (S4) using copper. After the surface of the conductor circuit is coarsened (S5), the conductor circuit is laminated on an insulating substrate for each single plate via the thin metal layer and is intimately adhered in a unitary structure by the application of heat and pressure (S7). Then, the single plate only is peeled off (S8), and the exposed thin metal layer is removed by etching (S9). The thin metal layer and the conductor circuit are electroplated at high speeds under the conditions of a liquid contact speed of 2.6 to 20 m/sec. and a current density of 0.15 to 4.0 Alcm 2 , so that a required intimate adhesion force is obtained between the thin metal layer and the resist mask. Further, the conductor circuit is provided with flexibility like that of rolled and annealed copper, thus making it possible to produce very thin and high-density conductor circuits having a thickness of smaller than 10 µm adapted not only to rigid printed wiring boards but also to flexible printed wiring boards.

    Abstract translation: 电路板导体制造方法使用通过电解形成的薄金属层，在具有预定粗糙度的导电性单板基板上保持1〜5微米的厚度，在薄金属的表面上形成抗蚀剂掩模 层，然后使用铜电导体导体电路。 在导体电路的表面粗大化之后，导体电路通过薄金属层层叠在每个单板的绝缘基板上，并通过施加热和压力而以一体结构紧密地粘附。 然后，仅剥离单个板，并通过蚀刻去除暴露的金属薄层。 薄金属层和导体电路在液体接触速度为2.6-20m / sec的条件下以高速电镀。 并且电流密度为0.15-4.00A /平方厘米，从而在薄金属层和抗蚀剂掩模之间获得所需的紧密粘附力。 导体电路具有类似于轧制和退火铜的柔性。

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