公开(公告)号：EP3013127A1

公开(公告)日：2016-04-27

申请号：EP15191149.2

申请日：2008-03-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shen, Xiaolan ,  Ye, Qingsong ,  Wei, Konggang

IPC: H05K1/02 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0218 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0298 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09627

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Abstract translation: 公开了印刷电路板及其设计方法。 该设计方法包括：在与外表面层相邻的内层处基于区域布线信号线; 将外表面层布置成没有布线或几条布线，并且通过通孔将外表面层互连，使得外表面层用作主地面; 并设置线宽和层高的参数以控制目标阻抗值。 印刷电路板包括外表面层和它们之间的两个内层。 与外表面层相邻的内层用于在区域的基础上布置信号线; 并且外表面层布置成没有布线或几个布线，并且通过通孔作为主地相互连接。 本发明还公开了使用印刷电路板的终端产品的主板。

公开(公告)号：EP2147464B1

公开(公告)日：2015-10-21

申请号：EP08736587.0

申请日：2008-04-25

Applicant: International Business Machines Corporation

Inventor： WEEKLY, Roger, Donell ,  HARIDASS, Anand ,  CHUN, Sungjun

IPC: H05K1/02 ,  H01L23/66 ,  H01L23/498 ,  H05K3/46 ,  H05K1/11

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

公开(公告)号：EP2205053B1

公开(公告)日：2013-11-20

申请号：EP10150191.4

申请日：2010-01-06

Applicant: Thales

Inventor： Ledain, Bernard ,  Henriot, Dominique

IPC: H05K3/38 ,  H05K3/46

CPC classification number: H05K3/462 ,  H05K3/244 ,  H05K3/3484 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378

Abstract: The method involves superimposing two layers, and metallizing two faces of each layer. An interlayer made of metallized thermoplastic material e.g. liquid crystal polymer, is arranged between the two layers. Holes are pierced within the two layers before the two layers are placed in contact with each other, and within the interlayer. The holes are metallized. A metal is applied on openings of the holes of the two layers, and another metal is applied on openings of the holes of the interlayer. The two layers and the interlayer are pressed for diffusion bonding of zones covered with the metals. An independent claim is also included for a printed circuit board comprising two superimposed metallized layers.

公开(公告)号：EP2081419B1

公开(公告)日：2013-08-07

申请号：EP09156903.8

申请日：2000-09-01

Applicant: Ibiden Co., Ltd.

Inventor： Inagaki, Yasushi c/o Ogaki-kita-kojou, Ibiden Co., Ltd. ,  Asai, Motoo c/o Ogaki-kita-kojou Ibiden Co., Ltd. ,  Wang, Dongdong c/o Ogaki-kita-kojou, Ibiden Co., Ltd., ,  Yabashi, Hideo c/o Ogaki-kita-kojou Ibiden Co., Ltd., ,  Shirai, Seiji c/o Ogaki-kita-kojou, Ibiden Co., Ltd.,

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

公开(公告)号：EP1937043A4

公开(公告)日：2012-10-24

申请号：EP06821879

申请日：2006-10-16

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI ,  TANAKA HIRONORI

IPC: H05K1/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

公开(公告)号：EP2259667A4

公开(公告)日：2012-06-13

申请号：EP08873646

申请日：2008-10-09

Applicant: IBIDEN CO LTD

Inventor： TAKAHASHI MICHIMASA ,  AOYAMA MASAKAZU

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/055 ,  H05K2201/09127 ,  H05K2201/09536 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49124

公开(公告)号：EP1968113A4

公开(公告)日：2012-06-13

申请号：EP06843746

申请日：2006-12-27

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49139

公开(公告)号：EP1811823B1

公开(公告)日：2012-06-06

申请号：EP05790482.3

申请日：2005-10-04

Applicant: Ibiden Co., Ltd.

Inventor： ASAI, Motoo, c/o IBIDEN CO., LTD. ,  KODAMA, Hiroaki, c/o IBIDEN CO., LTD. ,  YAMADA, Kazuhito, c/o IBIDEN CO., LTD.

IPC: G02B6/43 ,  H05K1/02 ,  H05K3/46

CPC classification number: G02B6/43 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061

Abstract: Disclosed is a small-sized multilayer printed wiring board wherein the degree of freedom in design is improved. Such a multilayer printed wiring board is easily applicable to high density wiring. Specifically disclosed is a multilayer printed wiring board wherein a plurality of insulating layers, a conductor circuit and an optical wiring are formed in layers and on which an optical device is mounted. Such a multilayer printed wiring board is characterized in that the optical wiring is formed between the insulating layers.

Abstract translation: 公开了一种小型多层印刷线路板，其中设计的自由度得到改善。 这种多层印刷线路板容易应用于高密度布线。 具体公开了多层印刷布线板，其中多层绝缘层，导体电路和光学布线形成为层并且光学器件被安装在该多层印刷布线板上。 这种多层印刷线路板的特征在于，在绝缘层之间形成光配线。

公开(公告)号：EP2146557B1

公开(公告)日：2012-05-16

申请号：EP09164411.2

申请日：2009-07-02

Applicant: Thales Holdings UK Plc

Inventor： Lawson, Graham ,  Loiselet, Emmanuel

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/09618 ,  H01L2924/00014

Abstract: An hermetically sealed integrated microwave circuit comprising a coplanar waveguide on a PCB (3, 4) electrically connected on one major surface to an IC, and thermally and electrically connected to a BGA (5) on its opposite major surface, in which the PCB has at least first and second printed layers, a microwave signal path extends from a ball of the BGA through a through-hole in both printed layers to the coplanar wave guide, and plural ground paths extend from balls (51) of the BGA (5) through first through-holes in the first printed layer of the PCB and through second through-holes of the second printed layer of the PCB, the first and second through-holes being non-coincident, to allow for an hermetic seal across the PCB whilst introducing a predetermined impedance in the PCB between the signal and ground paths.

公开(公告)号：EP1843650B1

公开(公告)日：2012-03-07

申请号：EP07013524.9

申请日：1999-07-30

Applicant: Ibiden Co., Ltd.

Inventor： Hirose, Naohiro ,  Noda, Kouta ,  Segawa, Hiroshi ,  En, Honjin ,  Tsukada, Kiyotaka ,  Ishida, Naoto ,  Asano, Kouji ,  Shouda, Atsushi

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/38 ,  B23K26/38

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165