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    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
    111.
    发明公开
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
    HALBLEITERBAUELEMENT UND VERFAHREN ZU SEINER HERSTELLUNG

    公开(公告)号：EP1498955A4

    公开(公告)日：2008-02-20

    申请号：EP03723122

    申请日：2003-04-16

    申请人： MATSUSHITA ELECTRIC IND CO LTD

    发明人： TAKAGI TAKESHI

    IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/80 ,  H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32105 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/7836 ,  H01L29/802

    摘要： A method for manufacturing a semiconductor device comprising the step of forming a lower gate electrode film on a semiconductor substrate (10) via a gate insulation film (11), forming an upper gate electrode film consisting of a material which is oxidized more slowly than this lower gate electrode film, patterning the upper and lower gate electrode films to form a gate electrode (12) having a lower gate electrode (12a) and an upper gate electrode (12b), introducing an impurity into the semiconductor substrate (10) to form a source/drain region (15), and oxidizing the side face of the lower gate electrode (12a) and that of the upper gate electrode (12b) to form an oxide film side wall (13) thicker in the gate length direction in the side of the lower gate electrode (12a) than in the gate length direction in the side of the upper gate electrode (12b).

    摘要翻译： 一种用于制造半导体器件的方法，该方法包括以下步骤：经由栅极绝缘膜（11）在半导体衬底（10）上形成下部栅电极膜，形成上部栅电极膜，该上部栅电极膜由比该电极更慢地氧化的材料构成 下栅电极膜，对上栅电极膜和下栅电极膜进行构图以形成具有下栅电极（12a）和上栅电极（12b）的栅电极（12），将杂质引入到半导体衬底（10）中以形成 源极/漏极区域（15）;以及氧化下部栅极电极（12a）的侧面和上部栅极电极（12b）的侧面，以形成在栅极长度方向上更厚的氧化物膜侧壁（13） （12a）侧的栅极长度方向上的栅极长度方向比上部栅极电极（12b）侧的栅极长度方向小。

    Low temperature sol-gel silicates as dielectrics or planarization layers for thin film transistors
    112.
    发明公开
    Low temperature sol-gel silicates as dielectrics or planarization layers for thin film transistors 审中-公开
    Niedrigtemperatur-Sol-Gel-Silicate als Dielektrika oder PlanarisierungsschichtenfürDünnschichttransistoren

    公开(公告)号：EP1879234A2

    公开(公告)日：2008-01-16

    申请号：EP07112365.7

    申请日：2007-07-12

    申请人： Air Products and Chemicals, Inc.

    发明人： Markley, Thomas John ,  Braymer, Thomas Albert ,  Kretz, Christine Peck ,  Weigel, Scott Jeffrey

    IPC分类号： H01L29/49

    CPC分类号： H01L29/78603 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/316 ,  H01L27/1248 ,  H01L27/1292 ,  H01L29/4908 ,  H01L51/0096 ,  H01L51/0525

    摘要： Traditionally, sol-gel silicates have been reported as being high temperature processable at 400C to give reasonably dense films that showed good leakage current densities ( -8 A/cm 2 ). Recently we have discovered that we are able to prepare films from particular combinations of sol-gel silicate precursors that cure at 135°C to 250°C and give good leakage current density values (9 x 10 -9 A/cm 2 to 1 x 10 -10 A/cm 2 ) as well, despite the decrease in processing temperatures. These are some of the first examples of silicates being cured at lower temperatures where the leakage current density is sufficient low to be used as low temperature processed or solution processable or printable gate dielectrics for flexible or lightweight thin film transistors. These formulations may also be used in the planarization of stainless steel foils for thin film transistors and other electronic devices.

    摘要翻译： 传统上，已经报道了溶胶 - 凝胶硅酸盐在40℃下是高温可加工的，以产生显示出良好的漏电流密度（<5×10 -8 A / cm 2）的相当致密的膜。 最近我们已经发现，我们能够从135℃至250℃固化的溶胶 - 凝胶硅酸盐前体的特定组合制备薄膜，并提供良好的漏电流密度值（9×10 -9 A / cm 2至1× 10 -10 A / cm 2），尽管处理温度降低。 这些是在较低温度下固化的硅酸盐的一些例子，其中漏电流密度足够低以用作柔性或轻质薄膜晶体管的低温处理或溶液可加工或可印刷的栅极电介质。 这些制剂也可用于薄膜晶体管和其它电子器件的不锈钢箔的平面化。

    Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device
    114.
    发明公开
    Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device 审中-公开
    一种电光装置，电子装置和方法，用于制造电光装置

    公开(公告)号：EP1850386A1

    公开(公告)日：2007-10-31

    申请号：EP07251523.2

    申请日：2007-04-05

    申请人： Epson Imaging Devices Corporation

    发明人： Sato, Takasi c/o Epson Imaging Devices Corporation ,  Morita, Satoshi c/o Epson Imaging Devices Corp.

    IPC分类号： H01L27/12 ,  H01L21/77 ,  G02F1/1362 ,  H01L29/49 ,  H01L29/786

    CPC分类号： G02F1/136213 ,  G02F1/136227 ,  G02F2001/13606 ,  H01L27/1255 ,  H01L29/4908 ,  H01L29/7869

    摘要： An electro-optical device includes a thin-film transistor that has a gate electrode, a gate insulating layer, and a semiconductor layer laminated in each of a plurality of pixel regions on an element substrate, a pixel electrode that is electrically connected to a drain region of the thin-film transistor, and a storage capacitor that has a lower electrode and an upper electrode facing each other with the gate insulating layer interposed therebetween. In the thin-film transistor, the gate electrode, the gate insulating layer, and the semiconductor layer are laminated sequentially in that order. The gate insulating layer includes a lower gate insulating layer having one or a plurality of insulating films, and an upper gate insulating layer having one or a plurality of insulating films. The lower gate insulating layer is formed to have a thickness sufficient to reduce parasitic capacitance of the thin-film transistor, and a portion of the lower gate insulating layer where the lower electrode and the upper electrode overlap each other is removed.

    摘要翻译： 电光装置的衬底包括一薄膜晶体管都具有一栅电极，栅极绝缘层，以及层叠在每个像素区域中的多个上元素的半导体层，像素电极做电连接到漏极 所述薄膜晶体管的区域，以及存储电容器确实具有下部电极和上部电极彼此面对置于其间的栅极绝缘层。 在该薄膜晶体管中，栅电极，栅绝缘层，和半导体层按该顺序依次层叠。 所述栅绝缘层包括具有一个或绝缘膜的多个，并且在上部栅具有一个或绝缘膜的多个绝缘层低的栅绝缘层。 下栅极绝缘层被形成为具有足够的厚度，以减少薄膜晶体管的寄生电容，并且下栅极绝缘层，其中所述下电极和所述上电极彼此重叠被去除的部分。

    Fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same
    115.
    发明公开
    Fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same 有权
    HerstellungsverfahrenfüreinDünnfilmystistor-Matrix-Substrat

    公开(公告)号：EP1804290A1

    公开(公告)日：2007-07-04

    申请号：EP06023036.4

    申请日：2006-11-06

    申请人： LG. Philips LCD Co. Ltd.

    发明人： Lim, Byoung Ho

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49

    CPC分类号： H01L27/1288 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/78633

    摘要： A method of fabricating a thin film transistor array substrate and a thin film transistor array substrate using the same for preventing a deterioration of a picture quality are disclosed. In the method of the thin film transistor array substrate, a transparent conductive material and a metal material are sequentially disposed on a substrate. A first mask process patterns the transparent conductive material and the metal material.
    The method forms the active layer of island-shape and the ohmic contact layer at an area which is overlapped with the gate electrode using the second mask process, and forms the source electrode and the drain electrode using the third mask process different from the second mask process. Accordingly, the gate electrode shields a light irradiated from the back light not to be thereby irradiated the light into the active layer of the TFT array substrate of the present invention. Thus, the TFT does not form a channel irregardless of a drive of the TFT array substrate, so that the TFT array substrate can remove a leakage of the pixel voltage signal charged into the pixel electrode. As a result, the TFT array substrate of the present invention can prevent a deterioration of a picture quality of the liquid crystal display device.

    摘要翻译： 公开了一种制造薄膜晶体管阵列基板的方法和使用该薄膜晶体管阵列基板的薄膜晶体管阵列基板，以防止图像质量的劣化。 在薄膜晶体管阵列基板的方法中，依次将透明导电材料和金属材料设置在基板上。 第一掩模工艺对透明导电材料和金属材料进行图案化。 该方法在使用第二掩模处理与栅电极重叠的区域形成岛状有源层和欧姆接触层，并且使用与第二掩模不同的第三掩模处理形成源电极和漏电极 处理。 因此，栅电极将从背光照射的光不会被照射到本发明的TFT阵列基板的有源层中。 因此，TFT不会形成TFT阵列基板的驱动的通道，因此TFT阵列基板能够消除充电到像素电极中的像素电压信号的泄漏。 结果，本发明的TFT阵列基板可以防止液晶显示装置的图像质量的劣化。

    Semiconductor device and method for manufacturing the same
    118.
    发明公开
    Semiconductor device and method for manufacturing the same 审中-公开
    Halbleiterbaulement undzugehörigesHerstellungsverfahren

    公开(公告)号：EP1717847A2

    公开(公告)日：2006-11-02

    申请号：EP06008978.6

    申请日：2006-04-28

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Isobe, Atsuo ,  Murakami, Satoshi ,  Takano, Tamae ,  Yamazaki, Shunpei

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/336

    CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/42384

    摘要： A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1 × 10 11 cm -3 or more and 1 × 10 13 cm -3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.

    摘要翻译： 本发明的半导体器件的制造方法包括以下步骤：在衬底上形成第一绝缘膜，在第一绝缘膜上形成半导体膜，通过对半导体膜进行等离子体处理来对半导体膜进行氧化或氮化 使用高频波，电子密度为1×10 11 cm -3以上且1×10 13 cm -3以下且电子温度为0.5eV以上且1.5eV以下的条件，形成第二 绝缘膜覆盖所述半导体膜，在所述第二绝缘膜上形成栅电极，形成第三绝缘膜以覆盖所述栅电极，以及在所述第三绝缘膜上形成导电膜。

    HIGH K DIELECTRIC FILM
    119.
    发明公开
    HIGH K DIELECTRIC FILM 审中-公开
    具有高k电介质膜

    公开(公告)号：EP1714324A2

    公开(公告)日：2006-10-25

    申请号：EP04796383.0

    申请日：2004-10-22

    申请人： Freescale Semiconductor, Inc.

    发明人： DROOPAD, Ravindranath

    IPC分类号： H01L29/49

    CPC分类号： H01L21/28194 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02269 ,  H01L21/28273 ,  H01L21/31604 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A dielectric layer (14, 22, 24, 32) comprised of lanthanum, lutetium, and oxygen that is formed between two conductors or a conductor (14, 20, 34) and a substrate (12, 26, 30). In one embodiment, the dielectric layer is formed over the substrate without the need for an additional interfacial layer. In another embodiment, the dielectric layer (22, 42, 46) is graded with respect to the lanthanum or lutetium content or in the alternative, may include aluminum. In yet another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer or between both the conductor and substrate and the dielectric layer. The dielectric layer is preferably formed by molecular beam epitaxy, but can also be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

    A method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
    120.
    发明公开
    A method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 审中-公开
    一种用于通过使用可移除的隔离层的制作在栅电极的两侧的空气间隙的方法

    公开(公告)号：EP1278247A3

    公开(公告)日：2006-06-14

    申请号：EP02392011.9

    申请日：2002-07-15

    申请人： Chartered Semiconductor Manufacturing Pte Ltd.

    发明人： Lap, Chan ,  Elgin, Quek ,  Ravi, Sundaresan ,  Yang, Pan ,  James, Yong Meng Lee ,  Ying, Keung Leung ,  Yelehanka, Ramachandramurthy Pradeep ,  Jia, Zhen Zheng

    IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L21/336

    CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

    摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor subsirate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted Tshaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted Tshaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.