公开(公告)号：EP1880353A4

公开(公告)日：2009-05-13

申请号：EP05742644

申请日：2005-05-09

Applicant: IBM

Inventor： STEWART IAN ,  KELLY FLOYD ,  BREEDVELT-SCHOUTEN ILSE

IPC: G06Q10/00

CPC classification number: G06Q10/109

Abstract: A time dimension management system is provided for managing time dimension of a data analyzing system for analyzing data stored in a data store based on a time data structure. The time dimension management system comprises a date selector controller and a calendar coordinator. The date selector controller is provided for controlling a date selector that presents to a user a standard calendar and a business calendar. The date selector controller has a standard calendar manager for managing presentation of the standard calendar for allowing the user to select a date on the standard calendar, and a business calendar manager for managing presentation of the business calendar to represent the time data structure that the data analyzing system uses, and allowing the user to select a date on the business calendar. The calendar coordinator is provided for coordinating the standard calendar manager and the business calendar manager to indicate a selected date on the standard calendar and the business calendar.

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：EP1356498A4

公开(公告)日：2009-05-13

申请号：EP01990114

申请日：2001-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ENGEL BRETT H ,  HOINKIS MARK ,  MILLER JOHN A ,  SEO SOON-CHEON ,  WANG YUN-YU ,  WONG HON WONG

IPC: H01K3/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/50 ,  H01L23/52 ,  H01L23/532 ,  H05K3/02

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.

公开(公告)号：EP1833229A4

公开(公告)日：2009-04-22

申请号：EP05816874

申请日：2005-12-15

Applicant: IBM

Inventor： OCHIAI KAZUMASA ,  KAMIJO NOBORU ,  AIHARA TOHRU

IPC: H04L29/10 ,  H01R13/71 ,  H04B3/54 ,  H04L12/28 ,  H04L12/46

CPC classification number: H04L63/08 ,  H01R27/00 ,  H04B3/54 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/5454

Abstract: [PROBLEMS] To safely and easily perform power cable communication with a server providing a desired service. [MEANS FOR SOLVING PROBLEMS] There is provided a communication relay device for relaying communication data between an information processing device and a communication network by utilizing a power cable where a communication signal is superimposed on a power signal. The communication relay device includes: an authentication information storage unit for storing authentication information for the communication relay device; a power plug which can be detachably attached to w power socket for connecting an electric device to the power cable; a connection detection unit for detecting that the power plug is connected to the power socket; an authentication unit for transmitting authentication information to the server via the power cable if the power plug is connected tot he power socket so that the server authenticates the communication relay device; and a communication relay unit for relaying the communication data from the information processing device for the communication network if the authentication by the authentication unit is sucessful.

公开(公告)号：EP1846947A4

公开(公告)日：2009-04-15

申请号：EP05852630

申请日：2005-12-02

Applicant: IBM

Inventor： VEREECKEN PHILIPPE M ,  BASKER VEERARAGHAVAN ,  CABRAL CYRIL JR ,  COOPER EMANUEL I ,  DELIGIANNI HARIKLIA ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  PARUCHURI VAMSI KRISHNA ,  SAENGER KATHERINE L ,  SHAO XIAOYAN

IPC: H01L21/302 ,  H01L29/745

CPC classification number: H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

Abstract: A method for electroplating a gate metal (9) or other conducting or semiconducting material on a gate dielectric (2) is provided. The method involves selecting a substrate (3, 4), dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be generated at an interface between the dielectric layer and the electrolyte solution or melt.

公开(公告)号：EP1587764A4

公开(公告)日：2009-04-15

申请号：EP03790042

申请日：2003-11-25

Applicant: IBM

Inventor： GOVINDARAJAN NATARAJAN ,  AHMAD UMAR ,  BEZAMA RASHID J ,  HUMENIK JAMES N ,  KNICKERBOCKER JOHN U ,  VALLABHANENI RAO V

IPC: B01L3/00 ,  B29C65/00 ,  B32B18/00 ,  C03B29/00 ,  C04B33/34 ,  C04B37/00

CPC classification number: B32B18/00 ,  B01J2219/00286 ,  B01J2219/00317 ,  B01L3/502707 ,  B01L3/5085 ,  B01L2200/12 ,  B01L2300/0816 ,  B01L2300/0819 ,  B01L2300/0887 ,  B01L2300/12 ,  B81B2203/0338 ,  B81B2203/0353 ,  B81C1/00119 ,  C04B35/645 ,  C04B2235/6567 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/62 ,  C04B2237/704

Abstract: A plate (10) for use in mixing and testing materials in the pharmaceutical industry is formed by a method in which apertures (22) (24) in a set of greensheets are formed by a material removal process, at least some of the apertures (25) being filled with a fugitive material (222) that escapes during sintering.

公开(公告)号：EP1371091A4

公开(公告)日：2009-04-01

申请号：EP01990800

申请日：2001-12-04

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. The control over the conductor resistance is obtained using a buried etch stop layer (56) having a second atomic composition located between the line and via dielectric layers (54', 58') of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask (60) which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：EP1450153A4

公开(公告)日：2009-03-18

申请号：EP02783676

申请日：2002-11-28

Applicant: IBM

Inventor： UDA MITSURU ,  TERAKAWA KAZUNARI ,  SUZUKI AKIRA ,  MORITA CHIAKI ,  YAMADA YASUHARU ,  HAYAND TERUHIKO

IPC: G01N21/956 ,  G03F7/20 ,  H01L21/027 ,  H01L21/66

CPC classification number: G03F7/70616 ,  G01N21/956 ,  G03F7/70641

Abstract: The profile error (deviation) of a pattern having an uneven section is detected simply and highly accurately. A pattern (32) inspection device for detecting the profile error of a pattern having an uneven section, comprising a plate (30) to mount a pattern thereon, light sources (40, 42, 44) capable of changing angles of light beams applied to the pattern within a range of 15 to 75 degrees with respect to the top surface of the pattern, and light receivers (52, 54) capable of receiving light beams reflected from the pattern at angles within a range of 15 to 75 degrees, characterized in that the profile error of the pattern is detected from quantities of reflected light from edges between the top surfaces and the side surfaces of respective portions of the pattern.

公开(公告)号：EP1444563A4

公开(公告)日：2009-03-11

申请号：EP02780516

申请日：2002-10-22

Applicant: IBM

Inventor： SMITH JACK ROBERT ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G06F1/26

CPC classification number: G06F1/3203

Abstract: In a first aspect, a method is provided for conserving power in a processing integrated circuit. This method includes the steps of calculating (401-408) power consumption for executing an instruction and data corresponding to the instruction; and executing (409, 410) the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of comparing (301, 302) a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and if the total power exceeds the power budget, freezing (304) execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution waSt frozen. Numerous other aspects are provided, as are systems and apparatus.

公开(公告)号：EP1586108A4

公开(公告)日：2009-03-04

申请号：EP02798556

申请日：2002-12-19

Applicant: IBM

Inventor： BREITWISCH MATTHEW ,  NOWAK EDWARD J

IPC: H01L27/11 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/11 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66765 ,  H01L29/785

Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118) and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.