公开(公告)号：EP2856691B1

公开(公告)日：2017-03-29

申请号：EP12877762.0

申请日：2012-05-29

申请人： NXP USA, Inc.

发明人： DOARE, Olivier ,  LANDEZ, Christophe

IPC分类号： H04L7/04 ,  H04L29/06

CPC分类号： H04L7/0008 ,  G06F13/4291 ,  H04L7/04

公开(公告)号：EP2813873B1

公开(公告)日：2017-03-29

申请号：EP14170945.1

申请日：2014-06-03

申请人： NXP USA, Inc.

发明人： Stephens, Tab A. ,  Pelley, Perry H. ,  McShane, Michael B.

IPC分类号： G02B6/125 ,  G02B6/13 ,  G02B6/136

CPC分类号： G02B6/136 ,  G02B6/125 ,  G02B6/131 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12104

摘要： An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer (103) on an optical backplane die wafer using an orientation-dependent anisotropic wet etch process to form a first recess opening (107) with angled semiconductor sidewall surfaces (106) on the optical waveguide semiconductor layer, where the angled semiconductor sidewall surfaces (106) are processed to form an optical backplane mirror (116) for perpendicularly deflecting optical signals to and from a lateral plane of the optical waveguide semiconductor layer.

公开(公告)号：EP2628249B1

公开(公告)日：2017-03-15

申请号：EP10805821.5

申请日：2010-10-15

申请人： NXP USA, Inc.

发明人： GAUTHIER, Laurent

IPC分类号： H04B1/40 ,  H04B7/04

CPC分类号： H04B1/40 ,  H04B1/406 ,  H04B7/0413

公开(公告)号：EP2858236B1

公开(公告)日：2017-03-01

申请号：EP14187537.7

申请日：2014-10-02

申请人： NXP USA, Inc.

发明人： Staudinger, Joseph ,  Srinidhi Embar, Ramanujam

IPC分类号： H03F3/19 ,  H03F3/21 ,  H03G3/30 ,  H03F1/02

CPC分类号： H03F1/0288 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/451 ,  H03F2200/66 ,  H03F2203/21175 ,  H03G3/3036

摘要： A device (500) includes an amplifier (503) having a first path (523) and a second path (517) and a first variable attenuator (521) connected to the first path. The device includes a controller (527) coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal (507) to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value.

摘要翻译： 装置（500）包括具有连接到第一路径的第一路径（523）和第二路径（517）和第一可变衰减器（521）的放大器（503）。 该装置包括耦合到第一可变衰减器的控制器（527）。 控制器被配置为确定到放大器的输入信号（507）的幅度。 当输入信号的幅度低于阈值时，控制器被配置为将第一可变衰减器的衰减设置为第一衰减值。 当输入信号的幅度高于阈值时，控制器被配置为将第一可变衰减器的衰减设置为第二衰减值。 第二衰减值小于第一衰减值。

公开(公告)号：EP2669942A3

公开(公告)日：2017-03-01

申请号：EP13169490.3

申请日：2013-05-28

申请人： NXP USA, Inc.

发明人： Carpenter, Burton J. ,  Higgins, III, Leo M.

IPC分类号： H01L23/36 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/42 ,  H01L2023/4056 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/45099

摘要： A packaged semiconductor device (100) comprises a package substrate (102) comprising a first package substrate contact (116, or 902) and a second package substrate contact (114 or 914), and a semiconductor die (104) over the package substrate. The semiconductor device further includes electrical connections (112) between signal contact pads of the die and the package substrate, and a heat spreader (134) that comprises a first heat spreader portion (128) which is electrically connected to a first signal contact pad (108) and the first package substrate contact (116 or 902) and provides an electrical conduction path and a thermal conduction path. A second heat spreader portion (132) provides an electrical conduction path between a second signal contact pad and the second package substrate contact and a thermal conduction path between the die and package substrate. An insulating layer (130 or 920) is positioned between the first and second heat spreader portions.

公开(公告)号：EP2654212B1

公开(公告)日：2017-03-01

申请号：EP13167459.0

申请日：2009-06-29

申请人： NXP USA, Inc.

发明人： Dehlink, Bernhard ,  Reuter, Ralf

IPC分类号： H04B1/16 ,  G01S7/40 ,  G01S3/48 ,  G01S13/93

CPC分类号： G01S7/4021 ,  G01S3/48 ,  G01S7/4052 ,  G01S13/931 ,  G01S2007/406 ,  G01S2007/4069 ,  G01S2007/4091 ,  G01S2013/9321 ,  G01S2013/9346

公开(公告)号：EP2452432B1

公开(公告)日：2017-03-01

申请号：EP10797771.2

申请日：2010-07-07

申请人： NXP USA, Inc.

发明人： SHIMONI, Eliezer

IPC分类号： H04B1/16 ,  H03G3/30

CPC分类号： H03G3/3068 ,  H04B1/713 ,  H04L27/22

公开(公告)号：EP3133735A1

公开(公告)日：2017-02-22

申请号：EP16182864.5

申请日：2016-08-04

申请人： NXP USA, Inc.

发明人： Jones, Jeffrey K.

IPC分类号： H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F1/02 ,  H03F1/56 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC分类号： H03F3/195 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L21/486 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49568 ,  H01L23/49827 ,  H03F1/0288 ,  H03F1/565 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/108 ,  H03F2200/165 ,  H03F2200/171 ,  H03F2200/181 ,  H03F2200/216 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/391 ,  H03F2200/42 ,  H03F2200/432 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/75 ,  H03F2203/21103 ,  H03F2203/21106 ,  H03F2203/21112 ,  H03F2203/21139 ,  H03F2203/21142 ,  H03F2203/21157

摘要： An amplifier module includes a module substrate. Conductive interconnect structures and an amplifier device are coupled to a top surface of the module substrate. The interconnect structures partially cover the module substrate top surface to define conductor-less areas at the top surface. The amplifier device includes a semiconductor substrate, a transistor, a conductive feature coupled to a bottom surface of the semiconductor substrate and to at least one of the interconnect structures, and a filter circuit electrically coupled to the transistor. The conductive feature only partially covers the semiconductor substrate bottom surface to define a conductor-less region that spans a portion of the bottom surface. The conductor-less region is aligned with at least one of the conductor-less areas at the module substrate top surface. The filter circuit includes a passive component formed over a portion of the semiconductor substrate top surface that is directly opposite the conductor-less region.

摘要翻译： 放大器模块包括模块衬底。 导电互连结构和放大器装置耦合到模块基板的顶表面。 互连结构部分地覆盖模块衬底顶表面以限定顶表面处的无导体区域。 放大器装置包括半导体衬底，晶体管，耦合到半导体衬底的底表面和至少一个互连结构的导电特征，以及电耦合到晶体管的滤波器电路。 导电特征仅部分地覆盖半导体衬底底表面以限定跨越底表面的一部分的无导体区域。 无导体区域与模块衬底顶表面处的至少一个无导体区域对准。 滤波器电路包括形成在半导体衬底顶表面的与无导体区域直接相对的部分上的无源部件。

公开(公告)号：EP2394299B8

公开(公告)日：2017-01-25

申请号：EP09786348.4

申请日：2009-02-03

申请人： NXP USA, Inc.

发明人： RENAUD, Philippe

IPC分类号： H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872 ,  H01L29/20 ,  H01L21/74 ,  H01L27/06 ,  H01L29/08

CPC分类号： H01L29/0847 ,  H01L21/746 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/872

摘要： A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers.

摘要翻译： 单片半导体结构包括一叠层。 所述堆叠包括基板; 由第一半导体材料制成的第一层; 以及由第二半导体材料制成的第二层。 第一层位于衬底和第二层之间，并且第一半导体材料和第二半导体材料中的至少一个含有III族氮化物材料。 该结构包括功率晶体管，其包括形成在层叠层中的主体; 位于所述第一层的面向所述第二层的一侧的第一电源端子; 至少部分地形成在所述基板中的第二电源端子; 以及栅极结构，用于控制在第一电力端子和第二电力端子之间通过电信号的主体的传播。 该结构还包括垂直肖特基二极管，包括：阳极; 包括衬底的阴极和阴极和阳极之间的肖特基势垒，肖特基势垒位于衬底和层叠层中的阳极层之间。

公开(公告)号：EP3073531A1

公开(公告)日：2016-09-28

申请号：EP16162195.8

申请日：2016-03-24

申请人： Freescale Semiconductor, Inc.

发明人： Min, Won Gi ,  Rodriquez, Pete ,  Yang, Hongning ,  Zuo, Jiangkai

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L27/0211 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality oftransistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.

摘要翻译： 一种器件包括半导体衬底，包括在彼此并联连接的半导体衬底中的第一多个晶体管结构的第一组成晶体管，以及包括在半导体衬底中并联连接的第二多个晶体管结构的第二组成晶体管 。 第一和第二组成晶体管彼此横向相邻设置并且彼此并联连接。 第一多个晶体管结构的每个晶体管结构在饱和区域中具有比第二多个晶体管结构中的每一个晶体管结构更低的电阻。