公开(公告)号：EP3049956A4

公开(公告)日：2017-04-12

申请号：EP14891599

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD

发明人： COL GERARD M ,  EDDY COLIN ,  HENRY G GLENN

IPC分类号： G06F15/163

CPC分类号： G06F9/226 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3836 ,  G06F12/0875 ,  G06F2212/452

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.

摘要翻译： 一种包括第一和第二保留站的装置。 第一保留站调度负载微指令，并且如果负载微指令是指定的从指定的资源而不是内核高速缓冲存储器检索操作数的指定负载微指令，则指示保持总线。 第二保留站耦合到保持总线，并且在分配第一加载微指令之后的数个时钟周期之后，发送依赖于负载微指令的一个或多个更小的微指令，并且如果在 所述保持总线，所述加载微指令是指定的加载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。 资源包括一个输入/输出（I / O）单元，配置为通过将乱序处理器耦合到I / O资源的I / O总线执行I / O操作。

公开(公告)号：EP3145113A1

公开(公告)日：2017-03-22

申请号：EP16191616.8

申请日：2008-03-25

申请人： INTEL Corporation

发明人： GUERON, Shay ,  FEGHALI, Wajdi ,  GOPAL, Vinodh ,  RAGHUNANDAN, Makaram ,  DIXON, Martin ,  KOUNAVIS, Michael ,  CHENNUPATY, Srinivas

IPC分类号： H04L9/06 ,  H04L9/08 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/14 ,  G06F9/30 ,  G06F9/38 ,  G06F21/60 ,  G11C7/10

CPC分类号： H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

摘要： A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a 'one round' pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

摘要翻译： 提供了一种用于通用处理器的灵活的指令集。 指令集包括对aes加密或解密执行“一轮”通过的指令，还包括执行密钥生成的指令。 立即可以用于指示128/192/256位键的密钥生成的循环数和密钥大小。 灵活的aes指令集可以充分利用流水线功能，因为它不需要跟踪隐式寄存器。

公开(公告)号：EP2870630A4

公开(公告)日：2016-07-27

申请号：EP13817338

申请日：2013-07-09

申请人： DE ROCHEMONT L PIERRE

发明人： DE ROCHEMONT L PIERRE

IPC分类号： H01L25/16 ,  H01L21/00 ,  H01L21/762 ,  H01L21/84 ,  H01L25/065 ,  H01L27/02

CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

摘要： A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

公开(公告)号：EP2433227B1

公开(公告)日：2015-09-16

申请号：EP10731653.1

申请日：2010-06-25

申请人： Simplivity Corporation

发明人： BOWDEN, Paul ,  BEAVERSON, Arthur, J.

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F17/30

CPC分类号： G06F12/1054 ,  G06F12/0246 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1408 ,  G06F17/30097 ,  G06F17/30949 ,  G06F17/30952 ,  G06F2212/2542 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/6032 ,  G06F2212/7211

公开(公告)号：EP2901289A1

公开(公告)日：2015-08-05

申请号：EP13840642.6

申请日：2013-09-19

申请人： Intel Corporation

发明人： CHUNG, Jaewoong ,  WU, Youfeng ,  WANG, Cheng

IPC分类号： G06F12/08 ,  G06F9/45

CPC分类号： G06F12/0888 ,  G06F9/4552 ,  G06F12/0246 ,  G06F12/0897 ,  G06F2212/452

摘要： Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.

公开(公告)号：EP2870630A2

公开(公告)日：2015-05-13

申请号：EP13817338.0

申请日：2013-07-09

申请人： De Rochemont, L. Pierre

发明人： De Rochemont, L. Pierre

IPC分类号： H01L25/16

CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

摘要： A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

摘要翻译： 混合片上系统提供安装在半导体载体芯片上的多个存储器和处理器管芯，其包含完全集成的电源管理系统，其以匹配或接近处理器核心时钟速度的速度切换DC电力，从而允许 片外物理内存与处理器之间的数据死亡。

公开(公告)号：EP2770446A4

公开(公告)日：2015-01-14

申请号：EP12878641

申请日：2012-12-28

申请人： HUAWEI TECH CO LTD

发明人： ZHONG YANHUI ,  ZHANG ZONGQUAN

IPC分类号： G06F17/30 ,  G06F3/06

CPC分类号： G06F3/0641 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/067 ,  G06F3/0673 ,  G06F12/0868 ,  G06F12/0875 ,  G06F2212/452

公开(公告)号：EP2616928A4

公开(公告)日：2014-02-26

申请号：EP11826042

申请日：2011-09-16

申请人： SOFT MACHINES INC

发明人： ABDALLAH MOHAMMAD

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3869 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452

摘要： A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

公开(公告)号：EP2433226A1

公开(公告)日：2012-03-28

申请号：EP10730310.9

申请日：2010-06-25

申请人： Simplivity Corporation

发明人： BEAVERSON, Arthur, J. ,  BOWDEN, Paul

IPC分类号： G06F17/30 ,  G06F11/14

CPC分类号： G06F12/1054 ,  G06F12/0246 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1408 ,  G06F17/30097 ,  G06F17/30949 ,  G06F17/30952 ,  G06F2212/2542 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/6032 ,  G06F2212/7211

摘要： A digitally signed file system in which data, metadata and files are objects, each object having a globally unique and content-derived fingerprint and wherein object references are mapped by the fingerprints; the file system has a root object comprising a mapping of all object fingerprints in the file system, such that a change to the file system results in a change in the root object, and tracking changes in the root object provides a history of file system activity.

公开(公告)号：EP0718758A3

公开(公告)日：1996-10-02

申请号：EP95480163.5

申请日：1995-11-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Mahin, Stephen William ,  Conor, Stephen Michael ,  Ciavaglia, Stephen J. ,  Moulton, Lyman Henry, III ,  Rich, Stephen Emery ,  Kartschoke, Paul David

IPC分类号： G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3812 ,  G06F9/3816 ,  G06F12/0886 ,  G06F2212/452

摘要： A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores addresses of lines which have been accessed for instruction fetching. In a system having modifiable instruction stream (i.e., store to instruction stream), when the CAM matches, the system must retire certain instructions, flush instructions and then fetch the modified instruction stream. Boundary identification logic examines a field in each cache byte to determine the nature of the byte. This field is initially cleared at the time the cache line is loaded and filled with the line is fetched. An anticipation buffer designed to minimize the circuitry necessary for fetches across cache lines is loaded with sequentially anticipated prefetched instructions from the cache. These anticipated instructions can then be concatenated by a fetch aligner.