公开(公告)号：EP0797245A3

公开(公告)日：1998-05-13

申请号：EP97104869

申请日：1997-03-21

申请人： TOSHIBA KK

发明人： BABA YOSHIRO ,  NARUSE HIROSHI

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/1037 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66666

摘要： A groove (4) is formed on a semiconductor substrate (1). A mask material layer (3) is so formed on the surface of the semiconductor substrate (1) as to open a groove (4) region. With the mask material layer (3) used as a mask, a semiconductor layer (10) is selectively formed on the semiconductor substrate (1) exposed with the inner wall surface of the groove (4). Then, the mask material layer (3) is removed. An insulating film (5) is formed on the semiconductor layer (10) formed on the inner wall surface of the groove (4) and the surface of the semiconductor substrate (1). The groove (4) is buried with a conductor (6).

公开(公告)号：EP0620600A2

公开(公告)日：1994-10-19

申请号：EP94302670.8

申请日：1994-04-14

申请人： Hughes Aircraft Company

发明人： Chang, Chen-Chi P. ,  Li, Mei F.

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  H01L29/60

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L29/4232

摘要： Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.

摘要翻译： 该阵列包括控制栅极（38），该控制栅极具有串联布置在浮动栅极（34）的节目部分（34a）和源极（18）之间的部分，以提供用于擦除的阈值电压控制。 浮动栅极（34）还具有从编程部分（34a）围绕通道（22）的一端延伸到源极（18）的擦除部分（34b）。 在擦除部分（34b）的端部（34c）和源极（18）的底层部分之间形成薄的隧道氧化物层（32），其能够通过Fowler-Nordheim隧道将浮动栅极（34）擦除 从施加电压低的端部（34c）通过氧化物层（32）到源极（18）。

公开(公告)号：EP0449418A3

公开(公告)日：1992-01-02

申请号：EP91301405.6

申请日：1991-02-21

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Sakamoto, Shinichi

IPC分类号： H01L29/10 ,  H01L29/784

CPC分类号： H01L29/4232

摘要： An insulated gate field effect device comprising: a first conductivity type semiconductor substrate having a main surface, said semiconductor substrate having a concave with a curved surface formed on said main surface, an insulating film formed on the main surface including said concave, first and second impurity regions of a second conductivity type formed in the vicinity of said main surface of said semiconductor substrate, and at one side and the other side of said concave, respectively, said first conductivity type region of said semiconductor substrate between said first and second impurity regions having a channel region formed along said concave, and a conductive layer formed above said channel region with said insulating film interposed therebetween.

公开(公告)号：EP0428738A4

公开(公告)日：1991-07-24

申请号：EP90907412

申请日：1990-05-09

申请人： OKI ELECTRIC INDUSTRY COMPANY, LIMITED

发明人： OKITA, YOSHIHISA OKI ELECTRIC INDUSTRY CO., LTD.

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732 ,  H01L29/78 ,  H01L29/73 ,  H01L21/335 ,  H01L27/092

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/82285 ,  H01L27/0823 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/66272 ,  H01L29/7325 ,  H01L29/78

摘要： Ions are selectively implanted into polycrystalline silicon for electrodes by utilizing low-temperature accelerated oxidation phenomenon in polycrystalline silicon having a high impurity concentration and acceleration energy dependency of impurity projection ranges of ion implantation. Therefore, there is no need of forming a mask resist pattern by photoengraving for every step of introducing impurities. Further, the base (source, drain) electrode is formed of polycrystalline silicon isolated by a selective oxidation method, the selectively oxidized film pertaining to the emitter (gate) region is removed, and a side wall spacer is formed on the inside of the emitter (gate) region, thereby making it possible to form the emitter (gate) of a reduced size.

公开(公告)号：EP2811527A2

公开(公告)日：2014-12-10

申请号：EP14153020.4

申请日：2014-01-29

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Lue, Hang-Ting ,  Chen, Wei-Chen

IPC分类号： H01L29/739 ,  H01L29/423

CPC分类号： H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

摘要： A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

摘要翻译： 双模式晶体管结构包括半导体本体。 器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可作为源极或漏极），以及邻近沟道区的n型端子区域（可用作源极或漏极） 通道区域的第二侧。 栅极绝缘体设置在沟道区域上的半导体本体的表面上。 栅极设置在沟道区域上的栅极绝缘体上。 第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。 可选地，可以在通道区域下方包括背栅。 可以使用偏置辅助门来在单个设备中选择n通道或p通道模式。

公开(公告)号：EP2550677B1

公开(公告)日：2014-06-18

申请号：EP11710487.7

申请日：2011-03-23

申请人： ABB Technology AG

发明人： RAHIMO, Munaf ,  KOPTA, Arnost ,  VON ARX, Christoph

IPC分类号： H01L29/423 ,  H01L29/739

CPC分类号： H01L29/7397 ,  H01L29/4232 ,  H01L29/7395

公开(公告)号：EP2643848A2

公开(公告)日：2013-10-02

申请号：EP11790940.8

申请日：2011-11-24

申请人： Centre National de la Recherche Scientifique (C.N.R.S.)

发明人： LARRIEU, Guilhem

IPC分类号： H01L21/335 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00 ,  H01L21/8232 ,  H01L29/739

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  B82Y40/00 ,  C01B32/15 ,  H01L21/02606 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/775 ,  Y10S977/762 ,  Y10S977/938

摘要： The invention relates to a process for fabricating a field-effect transistor device (20) implemented on a network of vertical nanowires (24), comprising the following steps: producing a source electrode (26) and a drain electrode (30) at each end of each nanowire (24) symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer (38) of conductive material around a layer (36) of dielectric material that surrounds a portion of each nanowire (24), a single conductive layer (38) being used for all the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer (32, 34) of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.

公开(公告)号：EP2550677A1

公开(公告)日：2013-01-30

申请号：EP11710487.7

申请日：2011-03-23

申请人： ABB Technology AG

发明人： RAHIMO, Munaf ,  KOPTA, Arnost ,  VON ARX, Christoph

IPC分类号： H01L29/423 ,  H01L29/739

CPC分类号： H01L29/7397 ,  H01L29/4232 ,  H01L29/7395

摘要： A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer.

公开(公告)号：EP2270843A3

公开(公告)日：2011-01-26

申请号：EP10184815.8

申请日：2002-08-16

申请人： Power Integrations, Inc.

发明人： Disney, Donald, R.

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/40 ,  H01L21/334 ,  H01L29/86 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/407 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  Y10S438/925

摘要： A method of fabricating a high-voltage transistor (80) on a substrate (81,100), the method comprising:
forming a plurality of parallel arranged drift regions (82) comprising a doped semiconductor layer of a first conductivity type interleaved with an insulating layer (88,102) surrounding a conducting layer, the conducting layers each comprising a field plate member (84,103);
forming source (87,105) and body regions (86,107), the body regions separating the source regions from the drift regions; and
forming insulated gates (90) adjacent the body regions, the insulated gates defining channels in the body regions between the source regions and the drift regions.

公开(公告)号：EP1440464A4

公开(公告)日：2010-07-21

申请号：EP02802458

申请日：2002-10-23

申请人： FAIRCHILD SEMICONDUCTOR

发明人： YEDINAK JOSEPH A ,  GLADISH JON ,  SHEKHAWAT SAMPAT ,  DOLNY GARY M ,  SHENOY PRAVEEN MURALEEDHARAN ,  LANGE DOUGLAS J ,  RINEHIMER MARK L

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L21/332 ,  H01L21/331

CPC分类号： H01L29/4232 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395