Abstract:
A technique for embedding a nanotube in a nanopore is provided. A membrane separates a reservoir into a first reservoir part and a second reservoir part, and the nanopore is formed through the membrane for connecting the first and second reservoir parts. An ionic fluid fills the nanopore, the first reservoir part, and the second reservoir part. A first electrode is dipped in the first reservoir part, and a second electrode is dipped in the second reservoir part. Driving the nanotube into the nanopore causes an inner surface of the nanopore to form a covalent bond to an outer surface of the nanotube via an organic coating so that the inner surface of the nanotube will be the new nanopore with a super smooth surface for studying bio-molecules while they translocate through the nanotube.
Abstract:
A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
Abstract:
A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.
Abstract:
Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture.
Abstract:
In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.