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    Method of fabricating semiconductor devices on a group iv substrate with controlled interface properties and diffusion tails
    41.
    发明公开
    Method of fabricating semiconductor devices on a group iv substrate with controlled interface properties and diffusion tails 审中-公开
    一种用于具有受控界面性质和扩散山麓IV族衬底上制造半导体器件的方法

    公开(公告)号：EP2428981A1

    公开(公告)日：2012-03-14

    申请号：EP11192479.1

    申请日：2007-07-19

    Applicant: Cyrium Technologies Incorporated

    Inventor： Puetz, Norbert ,  Fafard, Simon ,  Riel, Joseph, René, Bruno

    IPC: H01L21/20 ,  H01L21/3205 ,  H01L29/12 ,  H01L31/0256 ,  H01L21/02 ,  H01L33/00 ,  H01L31/074

    CPC classification number: H01L33/0066 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02546 ,  H01L31/074 ,  Y02E10/50

    Abstract: An opto-electronic device, such as a solar cell or a light emitting diode, is fabricated by forming a nucleating layer (22) on a p-type group IV layer (20). The nucleating layer (22) includes a III-V compound selected from the group consisting of AlAs, AlSb, AIN, Bas, BSb, GaN, GaSB, and InAs. A first III-V compound layer (24) is formed on the nucleating layer (22) and includes as group III element, at least one of gallium, indium, and aluminium, and as a group V element, phosphorus. The p-type group IV layer, which may be a p-type silicon layer, includes phosphorus atoms diffused from the first III-V compound layer, the concentration of the phosphorus atoms therein being a function of the thickness of the nucleating layer. The first III-V compound layer includes group IV atoms diffused from the p-type group IV layer, the concentration of the group IV atoms therein being a function of the thickness of the nucleating layer.

    Abstract translation: 一种光电器件，检查作为太阳能电池或发光二极管中，通过形成p型IV族层（20）上的成核层（22）制成。 该成核层（22）包括选自的AlAs，的AlSb，AlN，BAS，BSb的，氮化镓，GaSb和InAs构成中选择的III-V族化合物。 第一III-V族化合物层（24）形成在成核层（22）上，并且包括作为III族元素，镓中的至少一种，铟和铝，以及作为V族元素，磷。 在p型基IV层，其可以是p型硅层，包括从所述第一III-V族化合物层扩散磷原子，磷原子。其中是所述成核层的厚度的函数的浓度。 在第一III-V族化合物层包括从p型IV族层扩散IV族原子，IV族原子。其中是所述成核层的厚度的函数的浓度。

    Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates
    42.
    发明公开
    Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates 审中-公开
    Wachstum von mehrschichtigen Gruppe III-Nitridpuffern aufgroßflächigenSiliciumsubstraten und anderen Substraten

    公开(公告)号：EP2426699A1

    公开(公告)日：2012-03-07

    申请号：EP11178555.6

    申请日：2011-08-24

    Applicant: National Semiconductor Corporation

    Inventor： Bahl, Sandeep R. ,  Ramdani, Jamal

    IPC: H01L21/02

    CPC classification number: H01L21/762 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/7605 ,  H01L23/485 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

    Abstract translation: 一种方法包括在半导体衬底上形成第一外延层并蚀刻第一外延层以形成多个分离的第一外延区。 该方法还包括在蚀刻的第一外延层上形成第二外延层。 每个外延层包括至少一个III族氮化物，并且外延层共同形成缓冲器。 该方法还包括在缓冲器上形成器件层，并使用器件层制造半导体器件。 第二外延层可以包括基本上仅在第一外延区上的第二外延区。 第二外延层还可以覆盖第一外延区域和衬底，并且第二外延层可以被蚀刻也可以不被蚀刻。 可以在用于形成第二外延层的相同操作期间形成器件层。

    High voltage switching devices and process for forming same
    45.
    发明公开
    High voltage switching devices and process for forming same 有权
    Hochspannungsschaltungsvorrichtung und Herstellungsverfahrendafür

    公开(公告)号：EP2261988A2

    公开(公告)日：2010-12-15

    申请号：EP10182109.8

    申请日：2003-04-30

    Applicant: Cree, Inc.

    Inventor： Flynn, Jeffrey S ,  Brandes, George R ,  Vaudo, Robert P

    IPC: H01L29/20 ,  H01L29/778 ,  H01L21/335 ,  H01L29/872 ,  H01L29/868

    CPC classification number: H01L29/2003 ,  C30B25/02 ,  C30B29/40 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02664 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

    Abstract: 1. A microelectronic device structure is disclosed. It comprises:
    (a) a first GaN layer having a dopant concentration of not more than about 1×10 16 /cm 3 ;
    (b) a second GaN layer overlying said first GaN layer;
    (c) a third GaN layer overlying said second GaN layer, said third GaN layer having a dopant concentration of not more than about 1×10 16 /cm 3 ; and
    (d) at least one metal contact arranged over said third GaN layer;
    further comprising one of the following characteristics (i) or (ii):
    (i) the second GaN layer is conductive, and the at least one metal contact forms a metal-to-semiconductor junction with the third GaN layer; or
    (ii) the second GaN layer is of n-type conductivity, and a fourth GaN layer of p-type conductivity is disposed between the third GaN layer and the at least one metal contact.

    Abstract translation: 公开了一种微电子器件结构。 它包括：（a）掺杂剂浓度不大于约1×10 16 / cm 3的第一GaN层; （b）覆盖所述第一GaN层的第二GaN层; （c）覆盖所述第二GaN层的第三GaN层，所述第三GaN层的掺杂浓度不大于约1×10 16 / cm 3; 和（d）布置在所述第三GaN层上的至少一个金属接触层; 还包括以下特征（i）或（ii）之一：（i）所述第二GaN层是导电的，并且所述至少一个金属接触与所述第三GaN层形成金属与半导体结; 或（ii）第二GaN层是n型导电性的，并且在第三GaN层和至少一个金属接触之间设置p型导电性的第四GaN层。

    III-NITRIDE LIGHT EMITTING DEVICES GROWN ON TEMPALTES TO REDUCE STRAIN
    47.
    发明公开
    III-NITRIDE LIGHT EMITTING DEVICES GROWN ON TEMPALTES TO REDUCE STRAIN 有权
    在TEMPALTES上生长III-氮化物发光器件以减少应变

    公开(公告)号：EP2126985A2

    公开(公告)日：2009-12-02

    申请号：EP07859490.0

    申请日：2007-12-21

    Applicant: Philips Lumileds Lighting Company LLC ,  Koninklijke Philips Electronics N.V.

    Inventor： GRILLOT, Patrick N. ,  GARDNER, Nathan E. ,  GOETZ, Werner K. ,  ROMANO, Linda T.

    IPC: H01L33/00 ,  H01L21/20

    CPC classification number: H01L33/007 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262

    Abstract: In a Ill-nitride light emitting device, the device layers (10) including the light emitting layer are grown over a template (22, 26) designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is l(ain-plane -abulk) | / abulk. In some embodiments, the strain in the light emitting layer is less than 1%.

    Abstract translation: 在III族氮化物发光器件中，包括发光层的器件层（10）生长在模板（22,26）上，模板（22,26）被设计为降低器件中的应变，特别是在发光层中。 减少发光器件中的应变可以改善器件的性能。 该模板可以在常规生长模板可获得的晶格常数范围内扩大发光层中的晶格常数。 应变被定义如下：给定层具有对应于与该层具有相同组成的独立式材料的晶格常数的体晶格常数和对应于该层的晶格常数的面内晶格常数ain-面 在结构中生长。 层中的应变量为l（ain-plane-abulk）| / abulk。 在一些实施例中，发光层中的应变小于1％。

    SEMICONDUCTOR SUBSTRATE, FIELD-EFFCT TRANSISTOR, AND THEIR MANUFACTURING METHODS
    48.
    发明公开
    SEMICONDUCTOR SUBSTRATE, FIELD-EFFCT TRANSISTOR, AND THEIR MANUFACTURING METHODS 审中-公开
    HALBLEITERSUBSTRAT，FELDEFFEKTTRANSISTOR UND VERFAHREN ZU IHRER HERSTELLUNG

    公开(公告)号：EP1447839A4

    公开(公告)日：2009-11-04

    申请号：EP02755785

    申请日：2002-08-02

    Applicant: SUMCO CORP

    Inventor： MIZUSHIMA KAZUKI ,  SHIONO ICHIRO ,  YAMAGUCHI KENJI

    IPC: H01L21/20 ,  H01L29/10 ,  H01L29/80 ,  H01L21/205 ,  H01L21/336 ,  H01L29/161 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/802 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532 ,  H01L29/1054 ,  Y10S438/933

    Abstract: A semiconductor substrate, a field effect transistor and their manufacturing methods provided with, in order to lower penetrating dislocation density and reduce surface roughness to a practical level, an Si substrate 1, a first SiGe layer 2 on the Si substrate, and a second SiGe layer 3 arranged on the first SiGe layer either directly or with an Si layer in between; wherein, the first SiGe layer has a film thickness that is thinner than twice the critical film thickness, which is the film thickness at which dislocation occurs resulting in lattice relaxation due to increased film thickness, the Ge composition ratio of the second SiGe layer is at least lower than the intralayer maximum value of the Ge composition ratio in the first SiGe layer or in the first SiGe layer at the contact surface with the Si layer, and the second SiGe layer has an incremental composition region in which the Ge composition ratio gradually increases towards the surface at least in a portion thereof.

    Abstract translation: 半导体衬底，场效应晶体管及其制造方法为了降低穿透位错密度并将表面粗糙度降低到实用水平，Si衬底1，Si衬底上的第一SiGe层2和第二SiGe 层3直接布置在第一SiGe层上，或者在其间具有Si层; 其特征在于，所述第一SiGe层的膜厚比所述临界膜厚度的薄膜厚度薄，所述膜厚度是由于膜厚增加而发生错位而导致晶格松弛的膜厚度，所述第二SiGe层的Ge组成比在 最低于第一SiGe层或与Si层的接触面处的第一SiGe层中的Ge组成比的层内最大值，第二SiGe层具有Ge组成比逐渐增加的增量组成区域 至少在其一部分中朝向表面。

    Semiconductor device manufacturing method
    50.
    发明公开
    Semiconductor device manufacturing method 审中-公开
    半导体器件制造方法

    公开(公告)号：EP2104134A2

    公开(公告)日：2009-09-23

    申请号：EP09250644.3

    申请日：2009-03-06

    Applicant: Tohoku Techno Arch Co., Ltd. ,  Furukawa Co. Ltd. ,  DOWA Holdings Co., Ltd ,  Wavesquare Inc.

    Inventor： Takafumi, Yao ,  Meoung-Whan, Cho

    IPC: H01L21/20 ,  H01L33/00

    CPC classification number: H01L33/007 ,  H01L21/0242 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/20

    Abstract: A device manufacturing method comprises: a peeling buffer layer forming step of forming a peeling buffer layer (20, 30, 130) on an underlying substrate (10); a mask pattern forming step of forming, on the peeling buffer layer, a mask pattern (40, 140, 240) which partially covers the peeling buffer layer; a growth step of growing a group III nitride crystal from regions exposed by the mask pattern on a surface of the peeling buffer layer, thereby forming a structure (ST) in which a plurality of crystal members (60) are arranged with gaps (80, 81) therebetween so as to partially cover the peeling buffer layer and the mask pattern; a channel forming step of forming a channel (ETa, ETb, ETc, ... ) to supply a second etchant for the peeling buffer layer to the peeling buffer layer, by selectively etching the mask pattern using a first etchant for the mask pattern; and a separation step of separating the plurality of crystal members from the underlying substrate and separating the plurality of crystal members from each other by supplying the second etchant to the peeling buffer layer through the gaps and the channel and selectively etching the peeling buffer layer.

    Abstract translation: 一种器件制造方法，包括：在底层衬底（10）上形成剥离缓冲层（20,30,130）的剥离缓冲层形成步骤; 掩模图案形成步骤，在所述剥离缓冲层上形成部分地覆盖所述剥离缓冲层的掩模图案（40,140,​​240）; 在剥离缓冲层的表面上从由掩模图案露出的区域生长III族氮化物结晶的生长工序，由此形成多个结晶构件60以间隙80排列的结构ST， 81）以部分地覆盖剥离缓冲层和掩模图案; 通过使用用于掩模图案的第一蚀刻剂选择性地蚀刻掩模图案来形成通道（ETa，ETb，ETc，...）以将用于剥离缓冲层的第二蚀刻剂供应到剥离缓冲层的通道形成步骤; 以及分离步骤，通过将所述第二蚀刻剂经由所述间隙和所述沟道供应到所述剥离缓冲层，并且选择性地蚀刻所述剥离缓冲层，从而将所述多个晶体构件从所述底层基板分离并且将所述多个晶体构件彼此分离。

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