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164 条记录 (耗时 0.012 秒)

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    41.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路

    公开(公告)号：EP0920028A4

    公开(公告)日：1999-11-17

    申请号：EP96927191

    申请日：1996-08-16

    申请人： MITSUBISHI ELECTRIC CORP

    发明人： ARIKI TAKUYA

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/417

    CPC分类号： G11C7/1078 ,  G11C5/14 ,  G11C7/1051

    摘要： A semiconductor integrated circuit device (100) is provided with data outputting buffers (310.1 to 310.j) for respective data input-output terminals. Each buffer (310.i) is supplied with a power supply potential and a grounding potential from a power supply wiring and two systems of grounding wiring connected to independent power supply pads and grounding potential supply pads, respectively. When the device (100) outputs a signal of "H" level, each data outputting buffer supplies an electric current to the corresponding data outputting terminal through the two systems of power supply wiring. Therefore, the current flowing through each system of power supply wiring is suppressed and the noise generated in the power supply wiring and in the grounding wiring is reduced.

    OUTPUT CIRCUIT AND ELECTRONIC DEVICE USING THE CIRCUIT
    42.
    发明公开
    OUTPUT CIRCUIT AND ELECTRONIC DEVICE USING THE CIRCUIT 失效
    AUSGANGSSCHALTUNG UND ELEKTRONISCHE VORRICHTUNG DAMIT

    公开(公告)号：EP0780984A4

    公开(公告)日：1998-09-16

    申请号：EP96922222

    申请日：1996-07-04

    申请人： SEIKO EPSON CORP

    发明人： KUMAGAI TAKASHI ,  TOKUDA YASUNOBU

    IPC分类号： G11C7/10 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0948 ,  G11C11/41 ,  G11C11/417

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/00361 ,  H03K19/018521 ,  H03K19/0948

    摘要： An output circuit outputs data from an output terminal Dout after the potential at the terminal Dout is set at a prescribed intermediate value between the potential at the power source line and that at the ground line. The output circuit is provided with an output driving means (30) composed of first and second transistors (31 and 32). The first transistor (31) is provided with a first control terminal DP to which a first control signal is inputted and the second transistor (32) is provided with a second control terminal DN to which a second control signal is inputted. The output circuit is also provided with a setting means (22) which turns the transistors (31 and 32) off by controlling the first and second control signals and a short-circuiting means (50) which short-circuits either of the control terminals DP and DN to the output terminal Dout. Before the data are outputted, after the transistors (31 and 32) are turned off by the setting means (22), the potential of the output terminal Dout is set at the intermediate value by short-circuiting the control terminal DP or DN to the output terminal Dout by means of the short-circuiting means (50).

    摘要翻译： 输出电路，在将输出端子Dout设定为电源线电位与接地线电位之间的电位之后，输出来自输出端子Dout的数据信号。 输出电路包括由第一和第二晶体管31和32构成的输出驱动装置30.第一晶体管31具有输入第一控制信号的第一控制端子DP。 第二晶体管32具有输入第二控制信号的第二控制端DN。 它还包括设置装置22，其控制第一和第二控制信号以将第一和第二晶体管31和32设置为断开状态。 还包括使第一和第二控制端子DP，DN和输出端子Dout中的一个短路的短路装置50。 此外，在数据信号输出之前，晶体管31和32被设置装置22设置为截止状态，之后根据输出端子Dout的电位进行短路，并且输出端子被设置为 中间电位

    IMPROVED DATA OUTPUT BUFFER
    43.
    发明公开
    IMPROVED DATA OUTPUT BUFFER 失效
    VERBESSERTER AUSGANGSDATENPUFFER

    公开(公告)号：EP0714545A4

    公开(公告)日：1997-02-26

    申请号：EP95921591

    申请日：1995-06-01

    申请人： MICRON TECHNOLOGY INC

    发明人： MERRITT TODD

    IPC分类号： G11C11/417 ,  G11C7/10 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948 ,  G11C11/40

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K19/09429

    摘要： For use in a semiconductor circuit device, a uniquely-arranged tri-state output buffer (12) responds to a control signal generated in the semiconductor circuit device and a below-ground voltage level at an output terminal to prevent wasted drain current and substrate current, and reduce capacitance at the pull-up node driving the output terminal. The output buffer includes a power supply signal providing at least one voltage level with respect to common; an output terminal; a first circuit responding to the control signal by providing a first control voltage on a pull-up node; and a second circuit responding to the control signal by providing a second control voltage on a pull-down node. Further, the output buffer includes a pull-up transistor (60), responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a pull-down transistor (50), responsive to the voltage on the pull-down node and coupled between common and the output terminal.

    摘要翻译： 为了在半导体电路器件中使用，三态输出缓冲器响应半导体电路器件中产生的控制信号和输出端子处的地下电压电平，以防止浪费的漏极和衬底电流，并降低 上拉节点驱动输出端子。 所述输出缓冲器包括电源信号，所述电源信号相对于公共端提供至少一个电压电平，输出端，上拉节点，下拉节点，响应于所述控制信号的第一电路，通过提供第一控制电压 上拉节点和响应于控制信号的第二电路，通过在下拉上提供第二控制电压。输出缓冲器被设计为响应于输出端子上的电压电平基本上低于共同的水平，通过防止 从电源到输出端的电流。

    Semiconductor memory device
    46.
    发明公开
    Semiconductor memory device 失效
    Halbleiter-Speichereinrichtung。

    公开(公告)号：EP0453997A1

    公开(公告)日：1991-10-30

    申请号：EP91106361.8

    申请日：1991-04-19

    申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

    发明人： Takase, Shinsuke, c/o Intellectual Property Div. ,  Kato, Toshiya, c/o Intellectual Property Div.

    IPC分类号： G11C5/14 ,  G11C11/417

    CPC分类号： G11C5/14 ,  G11C11/417

    摘要： According to this invention, there is disclosed a semiconductor device in which a memory section and a logic section are arranged on the same semiconductor chip, comprising a high-resistance element (R₁, R₂, ..., R n ) constituting a memory cell (M₁, M₂, ..., M n ), a low-resistance line (L) connected to the high-resistance element (R₁, R₂, ..., R n ), a power source line (Lv1) serving as a power source path from a power source pad, a switching element (Sw) arranged between the low-resistance line (L) and the power source line (Lv1), and a control circuit for controlling the switching element (Sw).

    摘要翻译： 根据本发明，公开了一种半导体器件，其中存储部分和逻辑部分布置在同一半导体芯片上，包括构成存储器单元的高电阻元件（R1，R2，...，Rn） M1，M2，...，Mn），连接到高电阻元件（R1，R2，...，Rn）的低电阻线（L），用作电源的电源线（Lv1） 来自电源焊盘的路径，布置在低电阻线（L）和电源线（Lv1）之间的开关元件（Sw）以及用于控制开关元件（Sw）的控制电路。

    Improved random access memory employing complementary transistor switch (CTS) memory cells
    47.
    发明公开
    Improved random access memory employing complementary transistor switch (CTS) memory cells 失效
    改进的随机访问存储器使用补充晶体管开关（CTS）存储器单元

    公开(公告)号：EP0247324A3

    公开(公告)日：1990-10-10

    申请号：EP87104578.7

    申请日：1987-03-27

    申请人： International Business Machines Corporation

    发明人： Chan, Yuen Hung ,  Struk, James Robert

    IPC分类号： G11C11/411 ,  G11C11/416 ,  G11C11/417

    CPC分类号： G11C11/416 ,  G11C11/4113 ,  G11C11/417

    摘要： Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.