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公开(公告)号:EP4401125A3
公开(公告)日:2024-08-14
申请号:EP23216202.4
申请日:2023-12-13
申请人: NXP USA, Inc.
发明人: Lim, Swee Yean , Khoo, Ly Hoon , Liu, Huanhuan
IPC分类号: G11C5/04 , H01L23/13 , H01L23/31 , H01L23/498
CPC分类号: H01L2224/3222520130101 , H01L2924/1531120130101 , H01L2924/0020130101 , H01L23/3128 , H01L23/49816 , H01L23/13 , H01L2224/4822720130101 , G11C5/04 , H01L21/56 , H01L23/562 , H01L21/563
摘要: An apparatus includes a substrate including a planar surface. A die is attached to the planar surface of the substrate with an interposed die attach material. A solder mask is interposed between the die attach material and the planar surface, wherein the solder mask includes a recessed portion extending beneath a periphery of the die, the recessed portion filled with a molding underfill.
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公开(公告)号:EP4198751B1
公开(公告)日:2024-08-14
申请号:EP23150668.4
申请日:2008-04-11
CPC分类号: G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
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53.
公开(公告)号:EP4411737A1
公开(公告)日:2024-08-07
申请号:EP24154330.5
申请日:2024-01-29
发明人: BENHAMMADI, Jawad
CPC分类号: G11C16/22 , G11C7/24 , G11C13/0059 , G11C13/0064 , G11C16/3459 , G11C29/40 , G11C29/52 , G11C2029/440220130101
摘要: La présente description concerne un procédé de vérification d'une écriture d'une clé dans une mémoire non-volatile (104) comprenant les étapes suivantes: stocker dans un registre (206) d'une interface (106) de ladite mémoire, un premier code de redondance cyclique de ladite clé, précalculé ; écrire la clé de sécurité dans une zone (218) de la mémoire non-volatile (104); copier la clé de sécurité écrite dans ladite zone (218) vers un deuxième registre (212) de ladite interface (106); calculer un deuxième code de redondance cyclique sur un message formé par la clé de sécurité copiée à laquelle est adossé le premier code de redondance cyclique ; si le deuxième code de redondance cyclique est équivalent à la valeur nulle, considérer l'écriture de la clé de sécurité dans ladite mémoire non volatile (104) comme valide.
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公开(公告)号:EP4213028B1
公开(公告)日:2024-08-07
申请号:EP23150930.8
申请日:2023-01-10
IPC分类号: G06F12/02 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G11C29/02
CPC分类号: G06F12/0215 , G06F12/0238 , G06F2212/720320130101 , G06F2212/103220130101 , G06F2212/101620130101 , G06F2212/104120130101 , G06F2212/105620130101 , G11C16/26 , G11C16/08 , G11C16/0483 , G11C16/24 , G11C11/5642 , G11C16/32 , G11C2211/564320130101 , G11C2211/564220130101 , G11C29/028 , G11C29/021
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公开(公告)号:EP4073801B1
公开(公告)日:2024-08-07
申请号:EP20760586.6
申请日:2020-05-28
CPC分类号: G11C29/028 , G11C29/021 , G11C29/50008 , G11C2029/500420130101 , G11C2029/500620130101 , G11C29/1201 , G11C29/46 , G11C2029/440220130101 , G11C29/16 , G11C29/12005
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公开(公告)号:EP4362024A3
公开(公告)日:2024-07-31
申请号:EP24164272.7
申请日:2019-04-16
IPC分类号: G01R31/317 , G06F12/14 , G06F9/22 , G06F21/44 , G06F21/60 , G06F21/78 , G06F21/62 , G06F21/71 , G11C7/24 , G11C29/48 , G11C29/54 , G11C29/56 , G11C29/04 , G11C29/44
CPC分类号: G06F21/71 , G06F21/6209 , G11C29/56016 , G11C2029/040320130101 , G11C7/24 , G11C2029/440220130101 , G11C29/48 , G11C29/54 , G01R31/31719 , G06F12/1408 , G06F12/1458 , G06F2212/105220130101 , G06F21/608 , G06F21/44 , G06F2221/214320130101 , G06F2221/03320130101 , G06F21/78
摘要: An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.
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57.
公开(公告)号:EP4354440A3
公开(公告)日:2024-07-31
申请号:EP24159600.6
申请日:2020-05-22
发明人: TRAN, Hieu Van , LEMKE, Steven , TIWARI, Vipin , DO, Nhan , REITEN, Mark
CPC分类号: G11C11/54 , G11C11/5628 , G11C11/5635 , G06F17/16 , G06N3/065 , G06N3/048 , G06N3/044 , G06N3/045
摘要: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
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公开(公告)号:EP3824555B1
公开(公告)日:2024-07-31
申请号:EP19739790.4
申请日:2019-06-18
IPC分类号: H03K19/195 , G11C11/44
CPC分类号: H03K19/1952 , G11C11/44
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公开(公告)号:EP3723330B1
公开(公告)日:2024-07-31
申请号:EP19894659.2
申请日:2019-12-13
IPC分类号: G11C15/04 , G06F9/30 , G06F9/38 , H04L45/745
CPC分类号: G11C15/04 , G06F9/30047 , G06F9/3851 , G06F9/3802 , G06F9/30061 , H04L45/74591
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公开(公告)号:EP4404199A1
公开(公告)日:2024-07-24
申请号:EP23192608.0
申请日:2023-08-22
申请人: Kioxia Corporation
发明人: Komano, Yusuke
IPC分类号: G11C11/56
CPC分类号: G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/32
摘要: According to one embodiment, a semiconductor memory device includes a memory cell array (11A/11B) and a control circuit (14). The memory cell array (11A/11B) includes two or more memory cells. The control circuit (14) is configured to control a write operation of writing first data to the two or more memory cells and a read operation of reading the first data from the two or more memory cells. The control circuit (14) sets cell states of the two or more memory cells based on second data included in the first data in the write operation. The control circuit (14) converts read data into the first data based on the second data included in data read from the two or more memory cells in the read operation.
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