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    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    62.
    发明公开
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：EP2919273A1

    公开(公告)日：2015-09-16

    申请号：EP14803515.7

    申请日：2014-05-12

    申请人： Fuji Electric Co., Ltd.

    发明人： YOSHIMOTO, Atsushi

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739

    CPC分类号： H01L29/4236 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/768 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

    摘要： A method for manufacturing a semiconductor device includes a step of forming a trench (2) in a surface of a semiconductor substrate (1) of a first conductivity type in a depth direction; a step of forming a conductive layer (4) in the trench, with a first insulating film (3a) interposed therebetween; a step of dividing the conductive layer into a gate electrode (4a) and an in-trench wiring layer (4b) which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film (3e); a step of introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region (7) of a second conductivity type; and a step of selectively forming a main electrode region (8) of the first conductivity type in a portion of the channel forming region which is provided along an opening portion of the trench so as to come into contact with the opening portion.

    摘要翻译： 一种用于制造半导体器件的方法包括：在深度方向上在第一导电类型的半导体衬底（1）的表面中形成沟槽（2）的步骤; 在沟槽中形成导电层（4）的步骤，隔着第一绝缘膜（3a） 将导电层划分为在沟槽中彼此面对的栅极电极（4a）和沟槽内配线层（4b），并用第二绝缘体填充栅极电极和沟槽内配线层之间的间隙的步骤 电影（3e）; 将第二导电类型杂质引入到半导体衬底的整个表面中以形成第二导电类型的沟道形成区域（7）的步骤; 以及在沿着沟槽的开口部分设置的沟道形成区域的一部分中选择性地形成第一导电类型的主电极区域（8）以与开口部分接触的步骤。

    Nitride-based field-effect transistor and method of fabricating the same
    64.
    发明公开
    Nitride-based field-effect transistor and method of fabricating the same 审中-公开
    基于氮化物的场效应晶体管及其制造方法

    公开(公告)号：EP2835833A2

    公开(公告)日：2015-02-11

    申请号：EP14179908.0

    申请日：2014-08-05

    申请人： Seoul Semiconductor Co., Ltd.

    发明人： Takeya, Motonobu

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/20 ,  H01L29/423 ,  H01L29/08 ,  H01L29/207 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L23/373

    CPC分类号： H01L21/0254 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02639 ,  H01L21/02647 ,  H01L23/367 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/4958 ,  H01L29/66666 ,  H01L29/7828 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a GaN-based transistor including source electrodes (72), first switch semiconductor layers (40) of a first conductivity type formed under the respective source electrodes, second switch semiconductor layers (50) of a second conductivity type formed under the respective first switch semiconductor layers, third switch semiconductor layers (60) of the first conductivity type configured to surround lower parts of the second switch semiconductor layers and sides of the first switch semiconductor layers and the second switch semiconductor layers, gates (75, 76) each having vertical faces or inclined faces in which a channel is formed on sides of the first switch semiconductor layer and the second switch semiconductor layer, gate insulating layers (74) formed under the gates, and a drain electrode (20) electrically coupled to the source electrodes along a flow of charges in a vertical direction that passes through the channels.

    摘要翻译： 本发明公开了一种GaN基晶体管，其包括源电极（72），形成在各个源电极下方的第一导电类型的第一开关半导体层（40），形成在各个源电极下方的第二导电类型的第二开关半导体层 第一开关半导体层，第一导电类型的第三开关半导体层（60），其被配置为围绕第二开关半导体层的下部以及第一开关半导体层和第二开关半导体层的侧面，栅极（75,76）各自 具有其中在第一开关半导体层和第二开关半导体层的侧面上形成沟道的垂直面或倾斜面，形成在栅极下方的栅极绝缘层（74）以及电耦合到源极 电极沿着通过通道的垂直方向上的电荷流动。

    Electrochemically-gated field-effect transistor, method for its manufacture, its use, and electronics comprising said field- effect transistor
    65.
    发明公开
    Electrochemically-gated field-effect transistor, method for its manufacture, its use, and electronics comprising said field- effect transistor 审中-公开
    电化学控制场效应晶体管，用于其制造方法，及其用途和该场效应晶体管的电子

    公开(公告)号：EP2811525A1

    公开(公告)日：2014-12-10

    申请号：EP13401025.5

    申请日：2013-03-14

    申请人： Karlsruher Institut für Technologie

    发明人： Dasgupta, Subho ,  Hahn, Horst

    IPC分类号： H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L27/12

    CPC分类号： H01L29/4908 ,  B82Y10/00 ,  H01L21/02288 ,  H01L27/1292 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/7869

    摘要： The present invention relates to an electrochemically-gated field-effect transistor (FET) in which the channel length is independent from the printing resolution.
    The FET comprises an arrangement (11) placed on top of a substrate (10) which consists of a first electrode (1), a second electrode (2) and a transistor channel (4), located between the two electrodes (1, 2), an electrolyte (5), covering the transistor channel (4) completely, and a gate electrode (3).
    The first electrode (1), comprising a first solid or porous metallic conducting body, is placed on top of the substrate (10). The transistor channel (4), comprising a porous semiconducting material, is placed on top of the first electrode (1), partially covering the first electrode (1). The second electrode (2), comprising a second solid or porous metallic conducting body, is placed on top of the transistor channel (4) which is placed on top of the first electrode (1), at least partially covering the transistor channel (4). The electrolyte (5) penetrates at least through the transistor channel (4) down to the first electrode (1) while leaving a part of each electrode (1, 2) uncovered. The gate electrode (3), comprising a third solid or porous metallic conducting body, is placed in contact with the electrolyte (5) but without any contact to the arrangement (11).

    摘要翻译： 本发明涉及在电化学门控场效应晶体管（FET），其中信道长度是独立于打印分辨率。 放置在基板的顶部（10），该besteht第一电极的布置的FET包括：（11）（1），第二电极（2）和一个晶体管沟道（4），位于两个电极（1,2之间 ）（在电解质（5），覆盖所述晶体管通道（4）完全呼叫，和栅电极3）。 所述第一电极（1），包括第一固体或多孔金属导电体，被放置在基板（10）的顶部。 包括多孔半导体材料的晶体管通道（4），被放置在所述第一电极的顶（1）部分地覆盖所述第一电极（1）。 包括第二实心的或多孔的金属导电体的第二电极（2）中，对晶体管通道（4）的顶部上放置所有这些在第一电极（1）的顶部上放置至少部分地覆盖所述晶体管沟道（4 ）。 电解质（5）至少通过向下到（1），同时留下各个电极的一部分（1,2）未覆盖所述第一电极的晶体管沟道（4）穿透。 包括第三实心的或多孔的金属导电体的栅极电极（3），与所述电解质（5），但没有任何接触到装置（11）接触放置。

    Array substrate and method for fabricating array substrate, and display device
    68.
    发明公开
    Array substrate and method for fabricating array substrate, and display device 审中-公开
    Arraysubstrat und Verfahren zur Herstellung des Arraysubstrats und Anzeigevorrichtung

    公开(公告)号：EP2736077A1

    公开(公告)日：2014-05-28

    申请号：EP13193660.1

    申请日：2013-11-20

    申请人： Boe Technology Group Co. Ltd.

    发明人： Shi, Lei

    IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/786

    CPC分类号： H01L27/127 ,  H01L27/1251 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78648

    摘要： The present invention discloses an array substrate, a method for fabricating an array substrate, and a display device, the array substrate includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode. The present invention can form inversion layers at both upper and lower surfaces at the same time in a situation where a proper silicon film is selected, carrier concentrations in the inversion layers at both upper and lower surfaces increase rapidly with increase of gate voltage in a situation where the silicon film is fully depleted, and driving ability, and sub-threshold and frequency response characteristics of the array substrate are closer to an ideal state.

    摘要翻译： 本发明公开了阵列基板，阵列基板的制造方法以及显示装置，所述阵列基板包括：基底基板; TFT，栅极线，数据线和形成在基底基板上的像素电极，TFT包括：底栅极，第一栅极绝缘层，有源层，第二栅极绝缘层，顶栅极，栅极 隔离层和依次形成在基底基板上的源电极和漏电极; 其中，源电极和漏电极分别通过第一通孔和穿过栅极隔离层和第二绝缘层的第二通孔与有源层接触; 像素电极与漏电极接触。 本发明可以在选择适当的硅膜的情况下同时在上表面和下表面上形成反转层，在上下表面反转层中的载流子浓度随着栅极电压的增加而迅速增加 其中硅膜完全耗尽，驱动能力以及阵列基板的次阈值和频率响应特性更接近理想状态。

    A thin film transistor and manufacturing method thereof, an array substrate and a display device
    70.
    发明公开
    A thin film transistor and manufacturing method thereof, an array substrate and a display device 有权
    Dünnschichttransistorund Herstellungsverfahrendafür，ein Array-Substrat und eine Anzeigevorrichtung

    公开(公告)号：EP2722891A1

    公开(公告)日：2014-04-23

    申请号：EP13189461.0

    申请日：2013-10-21

    申请人： Boe Technology Group Co. Ltd.

    发明人： Liu, Xiang ,  Wang, Gang

    IPC分类号： H01L29/423 ,  H01L29/49 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/786 ,  H01L21/28008 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7869

    摘要： Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the electrical performance of the thin film transistor and improve the picture quality of images displayed by the display device. The thin film transistor includes: a substrate; a gate, a source, a drain and a semiconductor layer formed on the substrate; a first gate protection layer; a gate isolation layer; and a second gate protection layer. The first gate protection layer is at least partly located between the gate and the semiconductor layer, and is an insulating layer. The gate isolation layer is at least partly located between the first gate protection layer and the second gate protection layer, and is a conductive layer. The second gate protection layer is at least partly located between the gate isolation layer and the semiconductor layer, and is an insulating layer.

    摘要翻译： 本发明的实施例提供薄膜晶体管及其制造方法，阵列基板和显示装置，以改善薄膜晶体管的电气性能并提高由显示装置显示的图像的图像质量。 薄膜晶体管包括：基板; 形成在基板上的栅极，源极，漏极和半导体层; 第一栅极保护层; 栅极隔离层; 和第二栅极保护层。 第一栅极保护层至少部分地位于栅极和半导体层之间，并且是绝缘层。 栅极隔离层至少部分地位于第一栅极保护层和第二栅极保护层之间，并且是导电层。 第二栅极保护层至少部分地位于栅极隔离层和半导体层之间，并且是绝缘层。