公开(公告)号：EP1890958B1

公开(公告)日：2009-04-01

申请号：EP06709056.3

申请日：2006-01-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： JOISTEN, Hélène ,  CUCHET, Robert ,  AUDOIN, Marcel ,  BARROIS, Gérard

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/0054 ,  B81B2201/0292 ,  B81B2203/0118 ,  B81B2203/058 ,  B81C2201/0132 ,  B81C2203/032 ,  Y10T428/24479

Abstract: The invention relates to a method for producing a component with a first face of a plate-shaped structure (2) involving the following steps: engraving a second face of the structure, which is opposite the first face, on a portion of its surface in order to define an area of reduced thickness (22), and; inclining the area of reduced thickness (22) with regard said structure (2). A composite of this type has a recess between the plate-shaped structure and the inclined area of reduced thickness. The inclined area can thus support active elements (10, 12) that function according to a direction defined by the inclination.

公开(公告)号：EP1764830A3

公开(公告)日：2009-02-18

申请号：EP05447238.6

申请日：2005-10-21

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)

Inventor： Beyer, Gerald

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

Abstract: The present invention relates to a method for the production of very small trenches in semiconductor devices.
The formation of these small trenches is based on chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in said first dielectric layer are converted locally and become etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.
The small trenches obtained by chemically changing the properties of a dielectric layer can be used as test vehicle to study barrier deposition, copper plating and seedlayer deposition within very small trenches (order 10-30 nm).

公开(公告)号：EP2006249A2

公开(公告)日：2008-12-24

申请号：EP08158646.3

申请日：2008-06-20

Applicant: FEI COMPANY

Inventor： Toth, Milos ,  Smith, Noel

IPC: B81C1/00

CPC classification number: B05C21/005 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0143 ,  H01J37/3053 ,  H01J37/317 ,  H01J2237/3174 ,  H01J2237/31744 ,  H01J2237/31749

Abstract: A method for fabrication of microscopic structures that uses a beam process, such as beam-induced decomposition of a precursor, to deposit a mask in a precise pattern and then a selective, plasma beam is applied, comprising the steps of first creating a protective mask upon surface portions of a substrate using a beam process such as an electron beam, focused ion beam (FIB), or laser process, and secondly etching unmasked substrate portions using a selective plasma beam etch process. Optionally, a third step comprising the removal of the protective mask may be performed with a second, materially oppositely selective plasma beam process.

Abstract translation: 应用一种制造微结构的方法，该方法使用光束过程，例如光束诱导的前体分解，以精确图案沉积掩模，然后选择性等离子束，包括以下步骤：首先产生保护掩模 使用诸如电子束，聚焦离子束（FIB）或激光工艺的光束过程在衬底的表面部分上，并且使用选择性等离子体束蚀刻工艺二次蚀刻未掩模的衬底部分。 可选地，包括去除保护掩模的第三步骤可以用第二种，实质上相对选择的等离子体束工艺进行。

公开(公告)号：EP1623457B1

公开(公告)日：2008-11-26

申请号：EP04751610.9

申请日：2004-05-06

Applicant: Unaxis USA Inc.

Inventor： WESTERMAN, Russell ,  JOHNSON, David

IPC: H01L21/66

CPC classification number: H01J37/32935 ,  B81C1/00587 ,  B81C2201/0132 ,  H01J37/32963 ,  H01L21/30655

Abstract: The present invention provides a method for establishing endpoint during an alternating cyclical etch process or time division multiplexed process. A substrate is placed within a plasma chamber and subjected to an alternating cyclical process having an etching step and a deposition step. A variation in plasma emission intensity is monitored using known optical emission spectrometry techniques. An amplitude information is extracted from a complex waveform of the plasma emission intensity using an envelope follower algorithm. The alternating cyclical process is discontinued when endpoint is reached at a time that is based on the monitoring step.

公开(公告)号：EP1898458A1

公开(公告)日：2008-03-12

申请号：EP07017501.3

申请日：2007-09-06

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Murayama, Kei ,  Shiraishi, Akinori ,  Sunohara, Masahiro ,  Taguchi, Yuichi ,  Koizumi, Naoyuki ,  Higashi, Mitsutoshi

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/055 ,  B81B7/007 ,  B81B2203/0353 ,  B81B2203/0384 ,  B81B2207/096 ,  B81C1/00103 ,  B81C2201/0132 ,  H01L21/486 ,  H01L23/13 ,  H01L23/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method for manufacturing a package which includes: an etching step of etching a silicon substrate (101; 201), and forming a via hole (103, 106; 203, 203A, 207) penetrating through the silicon substrate; and a step of embedding an electrically conductive material in the via hole (106; 207), and forming a viaplug (107; 208), characterized in that the etching step includes a first etching step of forming the via hole in a straight shape, and a second etching step of forming the via hole in a taper shape.

Abstract translation: 一种封装的制造方法，其特征在于，包括：蚀刻硅基板（101; 201）的蚀刻工序，形成穿过所述硅基板的通孔（103,106; 203,203A，207） 以及在所述通孔（106; 207）中嵌入导电材料并形成viaplug（107; 208）的步骤，其特征在于，所述蚀刻步骤包括以直线形状形成所述通孔的第一蚀刻步骤， 以及形成锥形形状的通孔的第二蚀刻步骤。

公开(公告)号：EP1770056A2

公开(公告)日：2007-04-04

申请号：EP06076692.0

申请日：2006-09-07

Applicant: Delphi Technologies, Inc.

Inventor： Chilcott, Dan W.

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00531 ,  B81B2203/033 ,  B81C2201/0132 ,  B81C2201/0142

Abstract: A technique (500) for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided (502). Next, a plurality of trenches are etched into the substrate with a first etch (508). Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches (510). Finally, a second etch is provided into the undercut trenches. The charging layer causes the second etch to laterally etch foots in the substrate between the undercut trenches (512). The footers undercut the substrate to release a portion of the substrate for providing a movable structure between the undercut trenches and above the footers.

Abstract translation: 用于制造微机电（MEM）结构的技术（500）包括多个步骤。 首先，提供基板（502）。 接下来，通过第一蚀刻（508）将多个沟槽蚀刻到衬底中。 然后，在每个沟槽的底部形成充电层以形成底切槽（510）。 最后，在底切沟槽中提供第二蚀刻。 充电层使得第二蚀刻在底切沟槽（512）之间横向蚀刻衬底中的脚。 底脚底切基板以释放基板的一部分，以在底切沟槽和页脚之上提供可移动结构。

公开(公告)号：EP1734000A2

公开(公告)日：2006-12-20

申请号：EP06076128.5

申请日：2006-05-30

Applicant: Delphi Technologies, Inc.

Inventor： Chilcott, Dan W.

IPC: B81C1/00

CPC classification number: B81C1/00944 ,  B81C2201/0132

Abstract: A process for making a microelectromechanical device having a moveable component defined by a gap pattern in a semiconductor layer of a silicon-on-insulator wafer (10) involves the use of a plurality of deep reactive ion etching steps at various etch depths that are used to allow a buried oxide layer (14) of the silicon-on-insulator wafer (10) to be exposed in selected areas before the entire moveable component of the resulting device is freed for movement. This method allows wet release techniques to be used to remove the buried oxide layer (14) without developing stiction problems. This is achieved by utilizing deep reactive ion etching to free the moveable component after a selected portion of the buried oxide layer (14) has been removed by wet etching.

Abstract translation: 一种用于制造具有由绝缘体上硅晶片（10）的半导体层中的间隙图案限定的可移动部件的微机电装置的方法涉及使用多个深反应离子蚀刻步骤，所述深反应离子蚀刻步骤在使用的各种蚀刻深度 允许绝缘体上硅晶片（10）的掩埋氧化物层（14）在所得到的器件的整个可移动部件被释放以便移动之前暴露在选定的区域中。 该方法允许湿式释放技术用于去除埋入氧化物层（14）而不产生粘性问题。 这是通过利用深反应离子蚀刻在通过湿法蚀刻去除掩埋氧化物层（14）的选定部分之后释放可移动部件来实现的。

公开(公告)号：EP1655610A2

公开(公告)日：2006-05-10

申请号：EP06001026.1

申请日：2000-04-14

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Oguchi, Takahiro, (A170) Intell. Property Dept.

IPC: G01P15/08

CPC classification number: G01C19/5719 ,  B81B2201/025 ,  B81C1/00579 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/159

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole (20) dry etching of an element substrate (3), and an electrically conductive material is used as an etching stop layer (18) during the dry etching.

Abstract translation: 一种制造外力检测传感器的方法，其中通过元件基板（3）的通孔（20）干蚀刻形成传感器元件，并且导电材料被用作蚀刻停止层（18）期间 干蚀刻。

公开(公告)号：EP1510864A2

公开(公告)日：2005-03-02

申请号：EP04026039.0

申请日：2000-07-13

Applicant: Input/Output, Inc.

Inventor： Yu, Lianzhong ,  Ried, Robert P. ,  Goldberg, Howard D. ,  Yu, Duli

IPC: G03F7/00

CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

Abstract: The present invention provides merged-mask processes for fabricating micromachined devices in general and mirrored assemblies for use in optical scanning devices in particular. A method of fabricating a three dimensional structure, comprising, providing a substrate, applying a layer of a first masking material onto the substrate, applying a layer of a second masking material onto the layer of the first masking material, patterning the layer of the second masking material, applying a layer of a third masking material onto the portions not covered by the patterned layer of the second masking material, the layer of the third masking material is at least as thick as the combined thickness of the layers of the first and second masking materials, patterning the layers of the first and third masking materials, etching the exposed portions of the substrate, etching the exposed portions of the layers of the first and third masking materials and etching the exposed portions of the substrate.

公开(公告)号：EP1196788B1

公开(公告)日：2004-12-22

申请号：EP00945370.5

申请日：2000-07-13

Applicant: Input/Output, Inc.

Inventor： YU, Lianzhong ,  RIED, Robert, P. ,  GOLDBERG, Howard, D. ,  YU, Duli

IPC: G01P9/04 ,  G01P15/135 ,  G02B26/00 ,  C23F1/00 ,  G03F7/26 ,  G03F7/00

CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

Abstract: The present invention provides merged-mask processes for fabricating micro-machined devices in general and mirrored assemblies for use in optical scanning devices in particular. The process includes (a) providing a substrate having a predetermined thickness; (b) applying a first masking layer on a first portion of the substrate and a second masking layer on a second portion of the substrate, said second masking layer being at least as thick as the first masking layer; (c) etching a portion of the second masking layer to provide a first exposed portion of the substrate; (d) etching the first exposed portion of the substrate to a first depth; (e) etching the second masking layer to provide a second exposed portion of the substrate; and (f) etching simultaneously the first exposed portion of the substrate to a second depth and the second exposed portion of the substrate to a first depth. The process further comprises patterning the first masking layer before applying the second masking layer to provide the second portion of the substrate for etching and etching the first masking layer to expose the second portion of the substrate. The first and second masking layers are applied prior to etching the substrate.

Abstract translation: 本发明提供了用于一般地制造微机械装置和特别是用于光学扫描装置的镜面组件的合并掩模工艺。 一种制造三维结构的方法，包括：提供衬底，将第一掩蔽材料层施加到所述衬底上，将第二掩蔽材料层施加到所述第一掩模材料的所述层上，将所述第二掩模材料的所述层 掩模材料，将第三掩模材料层施加到未被第二掩模材料的图案化层覆盖的部分上，第三掩模材料的层至少与第一和第二掩模材料的层的组合厚度一样厚 掩模材料，图案化第一和第三掩模材料的层，蚀刻衬底的暴露部分，蚀刻第一和第三掩模材料的层的暴露部分并蚀刻衬底的暴露部分。