公开(公告)号：EP1367645A3

公开(公告)日：2006-12-27

申请号：EP03253279.8

申请日：2003-05-23

申请人： FUJITSU LIMITED

发明人： Fujisawa, Tetsuya, c/o Fujitsu Limited ,  Matsuki, Hirohisa, c/o Fujitsu Limited ,  Igawa, Osamu, c/o Fujitsu Limited ,  Aiba, Yoshitaka, c/o Fujitsu Limited ,  Ikumo, Masamitsu, c/o Fujitsu Limited ,  Sato, Mitsutaka, c/o Fujitsu Limited

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L23/498 ,  H01L25/065 ,  H01L21/98 ,  H01L21/58 ,  H01L23/31

CPC分类号： H01L24/29 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/24265 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor device (10) circuit formation surfaces of each of a plurality of semiconductor chips (12, 13) can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate (11) via an adhesive layer (15) in a two-dimensional arrangement. A resin layer (14) is formed on the substrate (11) and located around the semiconductor elements. The resin layer (14) has the same thickness as a thickness of the semiconductor elements (12, 13). An organic insulating layer (16) is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A
rearrangement wiring layer (17) is formed on the organic insulating layer (16) and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

公开(公告)号：EP1367645A2

公开(公告)日：2003-12-03

申请号：EP03253279.8

申请日：2003-05-23

申请人： FUJITSU LIMITED

发明人： Fujisawa, Tetsuya, c/o Fujitsu Limited ,  Matsuki, Hirohisa, c/o Fujitsu Limited ,  Igawa, Osamu, c/o Fujitsu Limited ,  Aiba, Yoshitaka, c/o Fujitsu Limited ,  Ikumo, Masamitsu, c/o Fujitsu Limited ,  Sato, Mitsutaka, c/o Fujitsu Limited

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L23/498

CPC分类号： H01L24/29 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/24265 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor device (10) circuit formation surfaces of each of a plurality of semiconductor chips (12, 13) can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate (11) via an adhesive layer (15) in a two-dimensional arrangement. A resin layer (14) is formed on the substrate (11) and located around the semiconductor elements. The resin layer (14) has the same thickness as a thickness of the semiconductor elements (12, 13). An organic insulating layer (16) is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A
rearrangement wiring layer (17) is formed on the organic insulating layer (16) and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

摘要翻译： 在半导体器件（10）中，当半导体芯片并排布置时，多个半导体芯片（12,13）中的每一个的电路形成表面可以容易地位于均匀的水平，从而简化了布置布线的处理。 半导体芯片以二维布置经由粘合剂层（15）安装在基板（11）上。 树脂层（14）形成在基板（11）上并位于半导体元件周围。 树脂层（14）的厚度与半导体元件（12,13）的厚度相同。 在树脂层的表面和半导体元件的电路形成表面上形成有机绝缘层（16）。 在有机绝缘层（16）和半导体芯片的电极上形成重排布线层（17）。 外部连接端子通过布线布线层中的布线电连接到半导体元件的电路形成表面。