公开(公告)号：EP1430756A1

公开(公告)日：2004-06-23

申请号：EP02773693.3

申请日：2002-09-30

Applicant: INTEL CORPORATION

Inventor： MCCORMICK, Carolyn ,  SATO, Daryl ,  BOGGS, David ,  JESSUP, Rebecca ,  DUNGAN, John

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L2924/15151 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0094 ,  H05K2201/09381 ,  H05K2201/0959 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/0455 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: An apparatus that includes a substrate, one or more via in pads (202) in the substrate; and one or more vents (204) in at least one of the one or more via in pads (202).

公开(公告)号：EP1430755A1

公开(公告)日：2004-06-23

申请号：EP02799370.8

申请日：2002-08-07

Applicant: INTEL CORPORATION

Inventor： BOGGS, David ,  JESSEP, Rebecca ,  MCCORMICK, Carolyn ,  SATO, Daryl ,  DUNGAN, John

IPC: H05K1/02

CPC classification number: H05K1/0269 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/099 ,  H05K2203/163 ,  H05K2203/166 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T428/218 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A registration coupon (20) is provided for a printed circuit board or other substrate. The registration coupon (20) may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon (20) may include a registration hole (30) provided on the circuit board, a metal pad (60) and an anti-pad (40) provided on the circuit board about the registration hole (30), and a solder mask (70) covering the metal pad (60).

公开(公告)号：EP1430531A2

公开(公告)日：2004-06-23

申请号：EP02752766.2

申请日：2002-08-08

Applicant: INTEL CORPORATION

Inventor： MCCORMICK, Carolyn ,  JESSEP, Rebecca ,  DUNGAN, John ,  BOGGS, David ,  SATO, Daryl

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/1394 ,  H01L2224/05599

Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.