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公开(公告)号：EP3021647A1
公开(公告)日：2016-05-18
申请号：EP15190771.4
申请日：2015-10-21
Applicant: MediaTek, Inc
Inventor： Chang, Sheng-Ming , Liu, Chia-Hui , Lin, Shih-Chieh , Chen, Chun-Ping
IPC: H05K1/11
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A printed circuit board (20) includes a laminated core (210) including at least an internal conductive layer (L 2 , L 5 ), and a build-up layer (212, 214) on the laminated core (210). The build-up layer (212, 214) includes a top conductive layer (L 1 , L 6 ). Microvias (220a, 220b) are disposed in the build-up layer (212, 214) to electrically connect the top conductive layer (L 1 , L 6 ) with the internal conductive layer (L 2 , L 5 ). A power/ground ball pad array is disposed in the top conductive layer (L 1 ). The power/ground ball pad array includes power ball pads (302) and ground ball pads (402) arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area (2a, 2b) that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads.
Abstract translation: 印刷电路板（20）包括层压芯（210），所述层压芯在所述层压芯（210）上包括至少内部导电层（L2，L5）和积层（212,214）。 积层（212,214）包括顶部导电层（L1，L6）。 微孔（220a，220b）设置在积层（212,214）中以将顶部导电层（L1，L6）与内部导电层（L2，L5）电连接。 电源/接地球垫阵列设置在顶部导电层（L1）中。 电源/接地球垫阵列包括以固定球垫节距P排列成阵列的电源球垫（302）和接地球垫（402）。电源/接地球垫阵列包括4球垫单元区域（2a ，2b），其仅由一个地面球垫和三个电源球垫组成，或者仅由一个电源球垫和三个地球垫组成。
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2.发明公开
公开(公告)号：EP2801123A4
公开(公告)日：2015-10-21
申请号：EP12864500
申请日：2012-11-01
Applicant: CRAY INC
Inventor： KIM HYUNJUN , CONGER JEFFREY SCOTT , SCOTT GREGORY ERWIN
CPC classification number: H05K1/0225 , H05K1/0219 , H05K1/0222 , H05K1/0245 , H05K1/0298 , H05K1/114 , H05K1/115 , H05K3/4007 , H05K3/42 , H05K2201/093 , H05K2201/09336 , H05K2201/09609 , H05K2201/09618 , Y10T29/49155 , Y10T29/49165
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公开(公告)号：EP2056457B1
公开(公告)日：2013-05-01
申请号：EP07790880.4
申请日：2007-07-17
Applicant: Murata Manufacturing Co. Ltd.
CPC classification number: H03H9/725 , H01L2924/19105 , H01P1/047 , H03H9/0542 , H03H9/0576 , H03H9/72 , H05K1/0243 , H05K1/113 , H05K1/114 , H05K1/117 , H05K1/181 , H05K2201/1006 , H05K2201/10522 , H05K2201/10636 , Y02P70/611
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公开(公告)号：EP1435658B1
公开(公告)日：2010-05-26
申请号：EP02779905.5
申请日：2002-10-07
Applicant: Tokuyama Corporation
Inventor： YAMAMOTO, Reo , KAMIYAMA, Yoshihide
CPC classification number: H01L23/49811 , H01L23/15 , H01L23/49827 , H01L2924/0002 , H05K1/0206 , H05K1/0306 , H05K1/114 , H05K3/0008 , H05K3/0082 , H05K3/064 , H05K3/246 , H05K3/4061 , H05K2201/0317 , H05K2201/0347 , H05K2201/10674 , H05K2203/167 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
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5.发明公开Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels 审中-公开使用微通孔的行/列的在BGA连接网格的导体优化轨迹
公开(公告)号：EP1753275A3
公开(公告)日：2009-01-21
申请号：EP06300874.2
申请日：2006-08-10
Applicant: Alcatel Lucent
Inventor： Brown, Paul James
IPC: H05K1/11 , H01L23/498
CPC classification number: H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/114 , H05K3/429 , H05K2201/09227 , H05K2201/09509 , H05K2201/10734 , H01L2924/00
Abstract: A printed circuit board having micro-vias (MV) used to connect a portion of the contacts (10') in a selected row or column to the first internal layer of the board, thereby creating routing channels on the second and subsequent internal layers of the board between selected rows or columns of through-board vias (12') used to connect the remaining contacts and a BGA package adapted to be used with the printed circuit board.
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Patent Agency Ranking6.发明公开Alternating micro-vias and through-hole vias for a BGA interconnect grid in order to create improved PCB routing channels 审中-公开在BGA接头光栅交替微通孔和通孔的排列为一个优化的导体轨道当然
公开(公告)号：EP1753274A3
公开(公告)日：2009-01-14
申请号：EP06300871.8
申请日：2006-08-09
Applicant: Alcatel Lucent
Inventor： Brown, Paul James
IPC: H05K1/11 , H01L23/498
CPC classification number: H05K1/114 , H01L21/50 , H01L23/49816 , H01L2924/0002 , H05K3/429 , H05K2201/09227 , H05K2201/09509 , H05K2201/097 , H05K2201/10734 , H01L2924/00
Abstract: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias (12') and micro-vias (MV) used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.
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公开(公告)号：EP1895589A2
公开(公告)日：2008-03-05
申请号：EP07122506.4
申请日：1998-09-28
Applicant: IBIDEN CO., LTD.
CPC classification number: H01L23/50 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15173 , H01L2924/15311 , H05K1/0271 , H05K1/114 , H05K1/116 , H05K3/3457 , H05K3/4602 , H05K3/4644 , H05K2201/09472 , H05K2201/09509 , H05K2201/09627 , H05K2201/09781 , H05K2201/10734 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
Abstract: The invention relates to a package board composed as a multi-layer wiring board, comprising a plurality of conductor circuits (158U,158D) formed in an outermost layer, an insulating layer (150) for supporting a plurality of said conductor circuits formed in said outermost layer and a plurality of inner layer conductor circuits formed under said insulating layer, wherein a plurality of said inner layer conductor circuits are a power supply layer (58U) and/or a ground layer (58D), a soldering bump (76U,76D) is formed, through said insulting layer, on each via-hole (160U,160D) connected to an inner layer conductor circuit.
Abstract translation: 本发明涉及一种作为多层布线板构成的封装板，包括形成在最外层的多个导体电路（158U，158D），用于支撑形成在所述第一层中的多个所述导体电路的绝缘层（150） 最外层和形成在所述绝缘层下面的多个内层导体电路，其中多个所述内层导体电路是电源层（58U）和/或接地层（58D），焊接凸块（76U，76D ）通过所述绝缘层形成在连接到内层导体电路的每个通孔（160U，160D）上。
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8.发明公开
公开(公告)号：EP1705967A3
公开(公告)日：2008-03-05
申请号：EP06300057.4
申请日：2006-01-23
Applicant: Alcatel Lucent
Inventor： Chan, Alex L.
IPC: H05K1/11
CPC classification number: H01L23/49816 , H01L23/50 , H01L2924/0002 , H05K1/0231 , H05K1/114 , H05K2201/10545 , H05K2201/10636 , H05K2201/10734 , Y02P70/611 , H01L2924/00
Abstract: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating, elongating and/or truncating the selected adjacent pairs and rotating their respective corresponding via pairs to adapt the spacing between the selected adjacent via pairs in the BGA land pattern and applying the capacitor pads to the selected via pairs. The selected adjacent via pairs and their respective link connectors are rotated, elongated and/or truncated in mutually opposite directions.
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公开(公告)号：EP1878326A2
公开(公告)日：2008-01-16
申请号：EP06740704.9
申请日：2006-04-05
Applicant: FCI
Inventor： MINICH, Steven , SMITH, Stephen, B. , MORLION, Danny
IPC: H05K1/00
CPC classification number: H01R12/737 , H01R12/716 , H01R12/724 , H01R13/6585 , H05K1/0219 , H05K1/0237 , H05K1/114 , H05K1/115 , H05K1/14 , H05K3/308 , H05K3/429 , H05K2201/044 , H05K2201/09236 , H05K2201/09627 , H05K2201/10189 , H05K2201/1059 , H05K2201/10659
Abstract: An orthogonal backplane connector systems having midplane footprints that provide for continuity of impedance and signal integrity through the midplane and allow for the same connector to be coupled to either side of the midplane. This design creates an orthogonal interconnect without taking up unnecessary PCB real estate. The midplane circuit board may include a first differential signal pair of electrically conductive vias disposed in a first direction, and a second differential signal pair of electrically conductive vias disposed in a second direction that is generally orthogonal to the first direction.
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10.发明公开Alternating micro-vias and through-hole vias for a BGA interconnect grid in order to create improved PCB routing channels 审中-公开在BGA接头光栅交替微通孔和通孔的排列为一个优化的导体轨道当然
公开(公告)号：EP1753274A2
公开(公告)日：2007-02-14
申请号：EP06300871.8
申请日：2006-08-09
Applicant: Alcatel
Inventor： Brown, Paul James
IPC: H05K1/11 , H01L23/498
CPC classification number: H05K1/114 , H01L21/50 , H01L23/49816 , H01L2924/0002 , H05K3/429 , H05K2201/09227 , H05K2201/09509 , H05K2201/097 , H05K2201/10734 , H01L2924/00
Abstract: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.
Abstract translation: 一种印刷电路板（PCB）组件，其具有电路层的包含外层和中间层与通孔用来转换网格的信号连接的部分（12“）和微通孔（MV），从而产生多个 一组在板的内部布局和安装在印刷电路板上的球栅阵列封装的通孔之间的对角线的布线通道。
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